ddarriba / mips_sim

MIPS simulator

mips_sim

MIPS simulator

mips_sim's Issues

Isolate CPU components

Detach Register Banks and ALU from CPU as a previous step for the flexible stage management. That way the pipeline stages will depend on CPU components and not on the CPU itself.

Compilation issues in Main branch with GCC 13

As mentioned in https://gcc.gnu.org/gcc-13/porting_to.html#header-dep-changes, some headers that were typically included by some C++ Standard Library headers are not included now in GCC 13.

As a consequence, you need to explicitly include in the two files where 'uint32_t' is used to avoid a compilation error: 'uint32_t' has not been declared.

I tried to attach a patch along with this message, but github apparently does not allow to upload files in issue messages in private repos :-? (maybe a config issue :-?). The simple patch is here: https://gac.udc.es/~emilioj/0001-Addressing-error-with-GCC-13-uint32_t-has-not-been-d.patch

Exception handling

Use special registers for handling CPU exceptions.

• BadVAddr: Memory address where exception occurred (e.g., unaligned or unallocated memory address)
• Status: Interrupt mask, enable bits and status when exception occurred
• Cause: Type of exception and pending interrupt bits (e.g., load from / store to an illegal address, arithmetic overflow)
• EPC: Address of instruction that caused the exception (return address from the exception handling routine at 0x80000080)