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Hardware implementation of the blake2 hash function

License: BSD 2-Clause "Simplified" License

Verilog 99.21% Coq 0.47% Makefile 0.01% Shell 0.31%

blake2's Introduction

blake2

This is a Verilog implementation of the BLAKE2 hash function. The specific function implemented is BLAKE2b.

Usage

Quick start

blake2_core #(
    .DIGEST_LENGTH(32)          // The length of the digest in bytes (20, 32, 48, 64)
) hasher (
    .clk(clk),                  // The module clock
    .reset_n(reset_n),          // Reset (active LOW)
    .init(init),                // Initialize the hasher (active HIGH)
    .next(next),                // Go to the next block (if data_length > 128 bytes)
    .final_block(final_block),  // This is the final block
    .block(block),              // The 128-byte block (padded if data_length < 128 bytes)
    .data_length(data_length),  // The byte length of the input data
    .ready(ready),              // HIGH when the core is ready to hash
    .digest(digest),            // The digest output
    .digest_valid(digest_valid) // HIGH when the digest output is valid
);

Further reading

blake2's People

Contributors

secworks avatar cyrozap avatar deekshadangwal avatar

Watchers

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Forkers

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