Repository is unfinished!!!!
This is an digital upsampler design that realise algorithm of multistage polyphase FIR filtering.
file | describtion |
---|---|
DPRAM.v |
Block Dual Port RAM |
MAC.v |
Multiplication and adder unit for vector convolution |
ControlUnit.v |
Control Unit of system with FSM |
AddrCalc.v |
Addres ALU |
- ✅ AudioBus
- ✅ RAM
- ✅ AddrCalc
- ✅ MAC (there is problem with sign extension of error word)
- [] Control Unit
- ✅ RegFile
- ✅ Allocation List Set with Programm Counter
- [] Top-level module
- [] simple testbench