defparam / bar-tender Goto Github PK

Using Vivado 2018.1
Loaded the project up (BAR-Tender.xpr)
Generate Bitstream
Got an error: Multiple block runs failed and synth_design ERROR

Also opening the project leads to this warning:

[Project 1-863] The design checkpoint file [Something]/BAR-Tender/fpga/vivado/BAR-Tender.srcs/sources_1/ip/pcie_7x_0/pcie_7x_0.dcp was generated for a block design or an IP or BD by an out of context synthesis run and should not directly be used as a source in a Vivado flow to refer to an IP source. As of 2017.1, the DCP from OOC runs will not contain XDC timing constraints because these are expected to be referred to by the IP .xci or .xcix file source. DCP files prior to 2017.1 will contain incorrect constraints because they were generated with default OOC clock period which will not likely match your top level clock constraints when used in the full design context.