dejianlin / fm-transmitter

FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic and so forth.

FM Transmitter

This is an FM transmitter using just an FPGA. This project uses SDR (Signal-Defined Radio) techniques to transmit an FM signal around 100MHz frequency band using just the FPGA, without any other device.

• The current code transmits the microphone input in an FM signal at 99MHz.

For that, we are using the Techs:

• CORDIC (COordinate Rotation DIgital Computer) algorithm
• CIC (Cascade Interpolation Comb) filter
• Sigma-Delta Modulators (currently just high-pass).

Thus, we already built some blocks to implement our FM transmitter:

• FM Modulator, essential block to modulate the input signal and put it into an intermediate frequency.

• DUC (Digital Up-Converter), block to send the intermediate signal to higher frequencies.

• HPDSM (High-Pass Delta-Sigma Modulator) DAC. With such, we are able to send high frequency signals through a 1-bit digital output, critical to our needs.

• Current Documentations:

  • CORDIC

• Instructions to setup this project on your device are coming!

Block Diagram

Milestones

• Blink led to test the Neek10 board
• Add CI
• Audio Loopback using data with sample rate of 48kHz
• Create test environment and add on CI
• Create and test sample interpolators to increase fs throughout the DUC (digital up-converter) chain, search for Comb filters
• Create and test the frequency shifter to the DUC chain (search for CORDIC).
  • Implement and test a CORDIC algorithm
  • Make sure it is possible to shift in frequency complex signals
• Create and test an HPSDM (High-Pass Delta-Sigma Modulator)
• Create and test an FM modulator in medium fs
• Create and test a DUC chain using the developed modules
• Test high-frequency sinusoid output on-board
• Test FM modulation and transmission with no input on-board
• test FM transmitter using sinusoidal input
• Test the FM transmitter on-board with audio input.
• (Optional) Replace AD from Codec by LPDSM (Low-pass Delta-Sigma Modulator)

Features

• Lint CI for Verilog
• Makefile with
  • Lint
  • Test using Pytest + Cocotb (also, Cocotb-test)
  • Compile code using quartus platform
  • Find and Program the Neek10 board, if attached on the computer
• Loopback using (Board sanity-check):
  • Onboarded Mic, which uses the ADC port for Max10 ADC protocol
  • Line out of Onboarded CODEC IC TLV320AIC3254
  • Sample rate 48kHz
  • Led meter to inform the audio energy
• Sdr Tools
  • Cic interpolator
  • Up-converter
    • CORDIC algorithm
    • Complete DUC.
  • FM modulator
• DA $\Sigma\Delta$ modulator
• AD $\Sigma\Delta$ modulator
• FM transmitter
• Use an LPSDM (Low-Pass Sigma-Delta Modulator) instead of using the built-in ADC from Max10.

CI

• Verilog lint;
• HDL unit tests using Cocotb + Pytest.

Unit testing

For the tests, it has been used python, using Cocotb + Pytest to perform the test benches.

It allows:

• Perform multiple types of tests using the same device
• Perform parametrized tests
• Test multiple devices separated
• Make assertions throughout the tests
• Save result files (as FFT, raw signal, etc)

Currently, there are tests for:

• reset_delay (test file)
  • Test if the parameter delay applies the correct delay
  • Assert if it is working
• sign_extend (test file)
  • Assert if it extends the signal of a set of values
  • Includes generated random values
• cic_interpolator (test file)
  • Test a set of sinusoids as input within different values of WIDTH and data length
    • Assert if the output sinusoids are correctly interpolated
    • Assert the output signal frequency
    • Assert the SNR for signals below $\frac{3}{4}\cdot \frac{fs}{2}$ are greater than 30dB
    • Save input and output results, including the FFTs
  • Test the impulsive response of the Cic implemented
    • Using 32-bit WIDTH
    • Save impulse response output, raw and FFT
  • FFT setup using hanning window to smooth side-lobes
• cordic (test file)
  • Test random complex input values (100 for each testcase) with random values and angles, including random rotational angles.
    • Assert whether the pipeline has the actual depth
    • Assert the circular rotation mode is working with the expected values, checking if the data was precise, error value less than 5.
    • Assert the circular vectoring mode is working with the same approach.
• hpdsm (test file)
  • Test input sinusoids with different widths and frequencies
    • Assert whether the output contains the sinusoid
    • Check if around the pass-band the noise is low
• fm modulator (test file)
  • Test input sinusoids with different widths and frequencies
  • Test different intermediate frequency and output sample rates
  • Test different Fm sensibility constant (K)
  • Demodulate the signal, decimate, and check the SNR output signal.
• digital up-converter (test file)
  • Test input sinusoids with different widths and frequencies
  • Test different intermediate frequency and output sample rates
  • Test with Fs out = Fclk
  • Check the SNR of the output signal.
• transmitter (test file)
  • Just test signal integrity in the output
  • TODO: test different input signals.