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matrix-voice-fpga

HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one

mic_array

DOA, VAD and KWS for ReSpeaker Microphone Array

mjpeg

simple parset

mjpegcapture-for-bbb

MJPEG VideoCapture for OpenCV

modexp

Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.

mxc-v4l2-tvin-tw6869-vdi

nrf8001-stm32f4

Nordic nrf8001 BLE example using ST STM32F4 MCU

odas

ODAS: Open embeddeD Audition System

open-source-fpga-bitcoin-miner

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

opensips

OpenSIPS is a GPL implementation of a multi-functionality SIP Server that targets to deliver a high-level technical solution (performance, security and quality) to be used in professional SIP server platforms.

openvino_python_samples

Sample Python Applications for DL Inference with OpenVINO

pl-mcu-epd

PlasticLogic microcontroller project

python-phonenumbers

Python port of Google's libphonenumber

react-native-ble-manager

React Native BLE communication module

recorder-gstreamer

roomdemo

Sample application using Room Persistence Library

rtspserverhost

sample-bluetooth-le-gattserver

sample_alsa_soc_driver

Sample code for Linux ALSA SoC sound card device driver.

speech_enhancement_mmse-stsa

A statistical model-based Speech Enhancement Using MMSE-STSA

spi_mem_programmer

Small (Q)SPI flash memory programmer in Verilog

tdoa

TDOA based on GCC-PHAT

test

test

testgit

tw6869

tw6869/65 media bridge driver

v4l2_mpeg

xilinx-serial-miner

Bitcoin miner for Xilinx FPGAs

yocto-config-variscite