dimembermatt / mppt-design

Design and documentation of a custom MPPT for LHR Solar. Created in part with Professor Alex Hanson's ECE 394J Power Electronics Class.

☀️ Sunscatter MPPT-Design - Gen 2 Maximum Power Point Tracker Board

Design and documentation of a custom MPPT for LHR Solar. Created in part with Professor Alex Hanson's ECE 394J Power Electronics Class.

---

Repository Structure

• datasheets - contains datasheets for major components of the Sunscatter.
• docs - contains documentation on how to build, test, and use the Sunscatter.
• fw - contains fw that is loaded onto the Sunscatter.
  • tests - test programs used to characterize and validate the Sunscatter.
  • src - main program used to run the Sunscatter.
  • inc - internally developed libraries specific for the Sunscatter.
  • lib - third party libraries used by the Sunscatter.
• hw
  • footprints - project specfic footprint association files for the Sunscatter.
  • models - 3d .step files for the PCB 3d viewer.
  • symbols - project specific symbol files for the Sunscatter.
  • vX_Y_Z - frozen versioning folder for PCB production files.
  • design files
• sim - contains a KiCAD project of the bare DC-DC converter of the MPPT, using SPICE parts for simulation.
• sw - contains relevant software for operating the automated design pipeline.
  • design_files
  • design_procedures

---

Maintainers

The current maintainer of this project is Matthew Yu as of 07/17/2023. His email is [email protected].

Contributors to the HW and FW encompass many dedicated students, including:

• Jacob Pustilnik
• Pranav Rama
• Sharon Chen

Special thanks to Professor Gary Hallock, who supervised the development and design of this project.

---

Versioning

This PCB is on unified version 0.2.0. Every time the schematic and/or layout is updated, this version number should go up. We use semantic versioning to denote between versions. See the changelog for more details.

---

TODO

Documentation

HW

FW

SW

Sim

mppt-design's Issues

Schematic: Update sensors to new range (neg current measurement)

Schematic: Add antisurge protection snubber circuitry for switching node

Schematic: Add temperature monitoring circuitry for high risk components

Define scope of SW optimization and simulation pipeline

What are the overarching goals and requirements for this project?

Given some design specifications, we want to

• find the optimal topology
  and components needed to build a converter that is:
  • maximally efficient
    • both broadly and
    • at maximum power transfer (the peak operating point)
  • maintains the desired safety factor
  • is within the specified input/output voltage/current ripple and
  • is effectively stable during open and closed loop operation
• visualize aspects of the optimal converter, including:
  • steady state operation, which involves input/output voltage
    mappings of:
    • duty cycle
    • current transfer
    • power transfer
    • losses across each component
    • temperature rise across each component
    • voltage and current ripple
    • efficiency
    • stability and time to settle within some statistical distribution
  • transient modeling of voltage and current nodes in response to some dynamic change.
• create a digital twin of a physical converter, that allows us to:
  • pair with different source/sink models
  • interface with higher level control models and
  • generate realistic dynamic simulations that can prove long duration
    efficiency and operation.

Based on the overarching goals, we have the following requirements:

• We shall be able to define requirements and operating
  specifications of the system, including:

  • the input and output model type and scope
  • the maximum acceptable input and output voltage and current
    ripple of the converter
  • the minimum acceptable stability of the converter
  • the minimum allowable safety factor of the converter
  • the maximum allowable cost and size budget of the converter

• We shall be able to provide a comprehensive and standardized set of components
  used in converter design, including the following:

  • FETs
  • schottky diodes
  • capacitors
  • inductors (cores + shape)

• We shall be able to select and design a converter from the
  following (but not exhaustive) list of topologies:

  • DC-DC converters
    • direct converter
      • asynchronous/synchronous buck/boost converter
      • four switch buck-boost converter
    • CCM and DCM operation
    • PFM operation
    • interleaved converters

Indirect DC-DC converters, DC-AC inverters, and AC-AC transformers are not
within the scope of this project.

• For each converter topology, we shall be able to identify a linear
  pathway for selecting components while minimizing the number of constraining
  variables.

• For each viable converter design (topology + components), we shall be able
  to generate estimated performance data in regards to the following attributes:

  • switching frequency
  • switch loss (switching versus conduction)
  • inductor loss (ripple versus conduction)
  • capacitor loss (ripple versus conduction)
  • switch temperature rise
  • inductor temperature rise
  • capacitor temperature rise
  • duty cycle
  • noise stability
  • component cost
  • component area

• For each viable converter design, we shall be able to assign a score or rank
  dependent on the estimated performance data, in particular:

  • total efficiency
  • total cost
  • total complexity (number of parts, distributors, etc)

• For each selected converter design, we shall be able to visualize its steady
  state and dynamic operation, including:

  • input/output maps of current, power transfer, efficiency, dead time, duty cycle
  • small signal stability analysis
  • large signal stability analysis
  • impulse response analysis

Sources:

• https://ocw.mit.edu/courses/6-334-power-electronics-spring-2007/888fe7fe65dbb6f11dc903f8caaa38f3_ch5.pdf
• https://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Erikson_DC_2_DC.pdf
• https://www.e3s-conferences.org/articles/e3sconf/pdf/2017/04/e3sconf_espc2017_14010.pdf
• https://www.youtube.com/watch?v=1iq-YA2ivos

Schematic: MCU template for STM32F446RETx

https://www.st.com/resource/en/datasheet/stm32f446re.pdf
https://www.st.com/resource/en/user_manual/dm00105823-stm32-nucleo-64-boards-mb1136-stmicroelectronics.pdf
https://www.st.com/resource/en/application_note/an1709-emc-design-guide-for-stm8-stm32-and-legacy-mcus-stmicroelectronics.pdf
https://www.st.com/resource/en/application_note/an4488-getting-started-with-stm32f4xxxx-mcu-hardware-development-stmicroelectronics.pdf

Schematic: Add heat sink support for passive cooling

Schematic: Update dc dc converter with optimizer design components

Evaluate optimizer design components for v0.3

Update existing HW project to KICAD 8

Schematic: Add fan header support for active cooling

Review codebase structure for optimization pipeline

Schematic: Add 12V - 5V - 3V3 power regulation circuitry

Schematic: Add extra hardware lockouts for OV/UV protection

Pipeline: Components package

Pipeline: Source/Sink package

Schematic: Modify gate driver to use 5V supply

Pipeline: Specs package

Propose v0.3.0 functional, safety, and performance requirements

From meeting notes:

Safety

• temperature monitoring of high risk components
  • gate driver
  • FETs
  • inductor
• antisurge protection
  • resistor + high voltage (max boost voltage * SF) diode path at switch node to handle voltage spike
    • yes it's a snubber circuit but no it's not supposed to be active during normal use
• extra hardware lockouts
• fan header support for additional active cooling (1W @ 12V) - M3 holes (default state on if unplugged)
• heat sink support for additional passive cooling
• potential new connector for ease of use and current capacity

Functional

• swap down from Nucleo to chip (aim for 50% size reduction) (pull from existing team sch)
• USB C connector, DCDC regulator (isolated? or with reverse polarity protection)
• noniso CAN (pull from existing team sch)
• higher performance MCU -> aim for 200 MHZ
• dedicated ICs for current and voltage monitoring instead of the STM ADC
  • use I2C/SPI protocol
  • 12 bit
  • 100 kHz sampling rate
  • possibly autobuffer
• shrink pcb size

Performance

• battery specs
  • 80V - 134V
  • use same model, assume 10A max input
• array specs
  • 0V - 80V VOC (25V - 70V, >100W)
  • 6.15A ISC
• 25% SF
• input inductor current ripple: N/A
• input capacitor voltage ripple: 1 V
• output capacitor voltage ripple: 1 V
• target efficiency: 99.5% at MPP

Cost Estimate for 5 PCBS

• PCB
  • 4 Layer
  • 2oz copper
  • both sides assembly
  • ~200 - 250$
• Additional Components
  • 500$
• Labor
  • priceless (worthless)

150 USD per PCB

Action Items

• 4/30: List of comprehensive tasks to be performed on optimization pipeline, simulation, sch/pcb, testing, etc (put on Github Project)
• 5/1: Preliminary schematic with BoM, begin initial review
• 5/4: Finalize schematic after full approval by (3) reviewers
• 5/4: Order initial test equipment
• 5/8: Preliminary layout, begin initial review
• 5/11: Finalize layout after full approval by (3) reviewers
• 5/12: Order pcbs and components
• 5/18: PCBs arrive, begin assembly
• 5/20: PCBs assembled, initial testing
• 5/30: Finish prelim testing, ship back to Austin

Schematic: Update to new CAN chip