djzenma / riscv-32ic-sim

RISC-V 32IC Disassembler and Simulator

RISCV-32IC-Sim

Design

Our purpose from the very start was to create a universal ISA simulator working cross-platform on any ISA the user gives to it. In fact, we have a human friendly configuration file which contains all the RV32IC needed information that we can replace if wanted to with any other instruction set and our simulator would still work.

Implementation

Our program is composed of these main classes and concepts: Fetcher, Decoder, Decompressor, Simulator (Executor). Thus, we process the raw binary file and fetch every instruction, then pass it to the Decoder which decodes the binary instructions into Instruction objects which contains all the information it needs about the instruction by matching with the yaml file(instruction name, format, opcode, funct3/funct4/funct7, register s1, register s2, register d, immediate). This allows the Decompressor to easily understand what are the different fields the instruction has and print it on screen. Afterwards, the simulator takes this same Instruction object with its encoded instruction and matches the name of the instruction with one of its keys mapping to the execution function, as we have an implementation for every instruction in the RV32IC in a class called Instructions (note that RV32C ‘s instructions map to its equivalent uncompressed instruction).

Limitations

Unfortunately, we didn’t finish the compressed isa. In addition to that, our simulator is hardcoded (unlike the Decoder, and the Disassembler) so it is only compatible with RV32IC architecture. We didn’t also have the time to implement a user interface or add additional support to any other ISA (for instance, MIPS) but all of that will come later. 

riscv-32ic-sim's Issues

Adding to the Config File

Add the following in the config file:

• Add Data Register File and Custom System Register File
• Add Operators based on data
• Create new instruction behavior based on the defined operators
• Add Custom Interupts given hardcoded interrupts (like NMI, TMR,...)

Template Configuration File Refactoring

• Remove 'key:op' from instruction group level to 'primaryKey' being at the top level of all formats.
• Remove secondary and precedence and replace with concatenation in code.
• Fix Immediate Formats.

Add an assembler

Simulator Bug

Simulator doesnt work on sample 6 and upwards

config file improvements part2

• Rename 'Name' to 'src' having as possible values either 'instr' or 'const'
  If 'const' then have a value field

• Support all possible architectures (16,32,...)

• Remove ImmediateLoadable

• If several architectures, must devine default architecture then foreach instruction that is not the default size, specify a mapping instr.

Add Soft Processor/Simulator