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0.0 2.0 1.0 19.99 MB

An ASIC running Pong.

License: Apache License 2.0

Makefile 0.20% C 0.53% Verilog 98.70% Python 0.44% Tcl 0.13%
asic caravel silicon ic fpga electronics verilog

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wrapped_pong's Issues

test results should propogate

pls add this line after each test recipe in your module test and caravel test

! grep failure results.xml

as cocotb prints error but returns 0. To make it return 1, need to grep for the error string.

remove output clock buffers

add this to config.tcl and re-harden. See thread in #mpw-2-prep for more details

set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0

roms missing when building caravel user project

Hi Eric,
not sure how to solve this in context of your project, but wanted to make a note.
The paddle and sine roms needed to be in the src directory for yosys to find them in the caravel context.

so what's interesting is that in this case the roms need to be in the same directory as the source files.
but they need to be elsewhere for the tests. What would be ideal is if we could just have them in the src location and somehow make the tests find them.

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