Serial Peripheral Interface

📝 Table of Contents

📙 overview
💻 Get Started
⚙️ How project Work
📷 Demo Screenshots
📁 File Structure
✨ Contributors

📙 overview

Design and implementation the following components of the SPI modules using verilog such that they match the requirements of the development testbench and match the SPI specifications:

Master
Slave
Self-Checking Testbenches for the Master and Slave.

🚀 Get Started

Clone the repository

git clone https://github.com/EslamAsHhrafSerial-Peripheral-Interface

Main File is

Serial-Peripheral-Interface/DevelopmentTB.v

Read Project Description to undertand project vey well

📜 How project Work

After each CLK the Master chose The Slave Again with CS with Enable One Slave and Disable the Other.
At Test Bench of the Master is to Send and Receive data from many Slaves at Same Time This Is Mainly Testing the ability Of the Exchange Between the Master and Many Slaves.
At Test Bench of The Slave Is to Receive Data from Master and makes shift Operation and Resend Shifted Data.
It wait the signal of start to begin the transmission (also the master will read "masterDataToSend" in order to send it to the slave).
And it takes 8 periods to send all data from the master to slave and slave to master.
We make it with 2 test cases different.

At Posedge

Both the Master and the slave take shifting operation which the Master writes data to the MOSI and the Slave Writes data to the MISO.

At Negedge

Both the Master and the Slave make sampling operation which the Master reads data From the MISO and The Slave reads data from the MOSI

How Data transfered between Master and Slave

the data is shown on the MOSI and MISO line. The start and end of transmission is indicated by the dotted green line, the sampling edge is indicated in orange, and the shifting edge is indicated in blue. Please note these figures are for illustration purpose only. For successful SPI communications, users must refer to the product data sheet and ensure that the timing specifications for the part are met

Multislave SPI configuration

📸 Demo Screenshots

Simulation Results of Development testbench

Waveform of Development testbench

Simulation Results of Master testbench

Waveform of Master testbench

Simulation Results of Slave testbench

Waveform of Slave testbench

🗃️ File Structure

Serial-Peripheral-Interface
├── Code
│   ├── Master.v
│   ├── Master.v.bak
│   ├── Master_tb.v
│   └── Master_tb.v.bak
├── CMP1030 Project Description.pdf
├── DevelopmentTB.v
├── DevelopmentTB.v.bak
├── Introduction-to-SPI-Interface.pdf
├── Lincense
├── README.md
└── Report .pdf