fredrik-reinholdsen / amaranth-minute-timer

An HDL implementation of a 60-second timer using 2 7-segment displays

7-Segment Minute Timer

This small project contains an HDL implementation of a 60-second timer, using a a 2-digit 7-segment display written in Amaranth/nMigen HDL language, based in Python, written for my ECPIX-5 development board by Lambda concept. The board features an ECP5-5G LFE5UM5G-85F FPGA, and is connected to a 2-digit 7-segment display, connected using two PMOD interfaces.

Build

The HDL can be built into a bitstream for the ECP-5 using the fully open source F4PGA toolchain, Yosys, nextpnr and project Trellis to build the final bitstream.

Simulation

To produce simulation waveform files, first install Amaranth

python -m pip install amaranth

and then simply execute either the timer.py or seven_segment.py to produce waveform .vcd files for the timer and seven-segment driver core respectively.

Programming

Also included is a .cfg file for the ECPIX-5 board that may be used to program the board using OpenOCD.

openocd -f openocd-ecpix5.cfg -c "init" -c "svf -quiet top.svf" -c "exit"