fujitsu / a64fx

A64FX

Features

A64FX is Fujitsu's Arm microprocessor which conforms to Armv8 + SVE.

This repository provides the documents and sample codes to develop Open Source Softwares like LLVM, Linux, Math libraries and so on.

Usage

git clone https://github.com/fujitsu/A64FX

Contact

• email: [email protected]

License

Copyright(c) 2019 Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. All rights reserved.

This product and related documentation are protected by copyright and distributed under licenses restricting their use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Fujitsu Limited and its licensors, if any.

The product(s) described in this book may be protected by one or more U.S. patents, foreign patents, or pending applications.

TRADEMARKS

Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Fujitsu and the Fujitsu logo are trademarks of Fujitsu Limited.

This publication is provided "as is" without warranty of any kind, either express or implied, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose, or noninfringement.

This publication could include technical inaccuracies or typographical errors. Changes are periodically added to the information herein; these changes will be incorporated in new editions of the publication. Fujitsu Limited may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

a64fx's Issues

A64FX_Microarchitecture_Manual_en_1.0.pdf Table 9-3

The table header of Table 9-3 is in Japanese (though the same table in Japanese PDF is in English).

A64fx Microarchitecture Manual 1.0 Figure 13-2

The last line of fig. 13-2 is as follows. (In both of English and Japanese version.)

b.ne loop    // Reload LBSY to x2 if LBSY = BST

The branch condition on the comment should be LBSY != BST .

How to control sector cache with assembly in dgemm kernel

Hi! Do you utilize the sector cache in the dgemm kernel? And could you please tell me how to control the sector cache with assembly? According to the documentation, it will benefit a lot in performance when controlling the sector cache. Actually I'm making some optimizations on Fugaku, but I don't know how to control the sector cache.

A64FX_PMU_Events_v1.2 The event unit that counts energy consumption is unknown

I don't know the unit of the following event, so I would like you to add it to the specification.
・EA_CORE
・EA_L2
・EA_MEMORY

Latency of `fadda`

According to the specification of the A64FX (v1.6), the latency of a fadda for doubles (<V> = D) with VL = 512 is 9 / 6 / ([1,2]9 / [1]6) x 6 / [1,2]9. I believe this should correspond to an overall latency of 9 + (9+6)*6 + 9 = 108, assuming the second micro-op can execute alongside the first. However, the actual latency of faddas as measure on hardware seems to be 72.

Could anyone please help me understand where this discrepancy is coming from?

-Ricardo

P.S. Here's the program I'm using to measure the latency of faddas:

//----------------------------------------------------------------------------
// Copyright (C) 2022 Ricardo Jesus, UK. All rights reserved.
//
// Redistribution and use of this software, with or without modification, is
// permitted provided that the following conditions are met:
//
// 1. Redistributions of this script must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//----------------------------------------------------------------------------

#include <iostream>
#include <chrono>
#include <cstdint>
#include <cstdlib>

extern "C" void kernel(std::uint64_t);

asm(R"(
    .global kernel
kernel:
    fadda d0, p0, d0, z0.d
    fadda d0, p0, d0, z1.d
    fadda d0, p0, d0, z2.d
    fadda d0, p0, d0, z3.d
    fadda d0, p0, d0, z4.d
    fadda d0, p0, d0, z5.d
    fadda d0, p0, d0, z6.d
    fadda d0, p0, d0, z7.d
    sub x0, x0, 1
    cmp x0, #0
    bgt kernel
    ret
)");

int main(int argc, char *argv[])
{
    using namespace std;

    const double clock = 1.8e9;  // GHz
    const uint64_t iters = 1000000ul;  // > 0
    const uint64_t insts = 8 * iters;  // match kernel asm

    auto start = chrono::steady_clock::now();
    kernel(iters);
    auto end = chrono::steady_clock::now();

    chrono::duration<double> elapsed_seconds = end-start;
    chrono::duration<double> lat = elapsed_seconds*clock/insts;

    cout << insts << " fadda in " << elapsed_seconds.count() << " seconds" << endl;
    cout << "Latency: " << lat.count() << " cycles" << endl;

    return 0;
}

Will the McKernel be open too?

In today vendor showdown at ISC2020 the slides showed the presence of a lightweight kernel called McKernel on PrimeHPC1000 systems.
Is it open source yet and if not do you plan to release it?
I am sorry if i am asking in the wrong place.