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A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

License: MIT License

SystemVerilog 66.48% C++ 0.79% Assembly 11.92% C 18.15% Shell 1.80% Python 0.73% Tcl 0.12%
asic cpu fpga hdl systemverilog rv32i rv32c rv32m rv32b rv32zfinx

apogeorv's Introduction

Hi there 👋

I'm currently studying Computer Engineering at University of Palermo (UNIPA). I love hardware related stuffs, in particular chip design (FPGAs, ASICs ...).

📧 How to reach me:

📚 Currently self studying:

  • RISC-V ISA
  • Embedded Systems
  • Microcontroller programming
  • Verification
  • C++ language

apogeorv's People

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