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gardners avatar gardners commented on July 30, 2024

Also happens with LDZ $DC00

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gardners avatar gardners commented on July 30, 2024

... and LDA $DC00

So is not related to the opcode, and applies to both CIAs and SDCARD controller.

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gardners avatar gardners commented on July 30, 2024

... but LDA $D000 is okay.

But then the VIC-IV reads on a separate port, which lends some credence to the idea that things are being latched when they shouldn't.

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gardners avatar gardners commented on July 30, 2024

Above commits try to fix latching of output for CIAs and SDCARD. Also, realised kickstart ROM has
a waitstate, so removing that, although it shouldn't have hurt.

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gardners avatar gardners commented on July 30, 2024

Building FPGA config using the workaround in commit 18a9924. Separating the glitching signals should solve the problem, if a little inelegantly.

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gardners avatar gardners commented on July 30, 2024

Have changed sector_buffer to an explicit block RAM to stop it being inferred as 4,096 1-bit registers. Now synthesises, and the previous odd behaviour has disappeared thanks to separating the kickstart read port from the iomapper read port. However the block ram based sector buffer is not working correctly. Writes to the sector buffer are having no effect, it seems.

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gardners avatar gardners commented on July 30, 2024

Fixed.

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