gdevic / a-z80 Goto Github PK

It seems like the M1 signal is pulled low during bus acknowledge, which would break DMA to IO devices, since they could interpret the I/O request as an interrupt acknowledge. I have no original Z80 on hand right now, but I checked using Z80 explorer that M1 should indeed be high when BUSACK goes low.

By Z-80 specification Data pins are sampled (latch-ed) in the beginning of T3 for Op-Code fetching or in the middle of T3 for Memory/IO read.
By this project implementation it ALWAYS are fetched in the middle of T2.
It's way to early! In the middle of T2 WAIT bus are sampled, and if it's LOW - extra Tw are added between T2 and T3 until WAIT go HIGH.
That's why Data pins always sampled in T3 and never in T2.
Why that? Does that is unspecified declination from specification in Z-80 chip or just error in that particular project?

The pdf of the schematic of the register file and at least another one are cropped. The pngs seems to be fine though.