gekkio / gb-ctr

Game Boy: Complete Technical Reference

Game Boy: Complete Technical Reference

Latest version rendered as PDF

gb-ctr's Issues

missing opcodes

Are you planning to add the missing opcodes?

RET cc=true - Cycle Duration

The M-cycle duration for conditional RET cc=true is listed as "4". I'm not sure if this is correct. PanDocs and the gblargg instr_timing test think that "5" is the correct answer.

Incorrect address of LY and LYC

In Chapter 4
PPU (Picture Processing Unit)

It should be 0xFF44 and 0xFF45.

No "data" in the bus timings for 0xFE00-0xFFFF

In the bus timing diagrams, there's no "data" block for the 0xFE00-0xFFFF range diagrams, both read and write. Is it by mistake, or there's something special about this range and data bits are passed in some other way?

gb-ctr/appendix/external-bus.tex

Line 85 in 9bc0999

Data & X 9Z \\

gb-ctr/appendix/external-bus.tex

Line 156 in 9bc0999

Data & X 9Z \\

Number of SP-- in PUSH rr

I'm still pretty new to those stuff so I could definitely be wrong, but.. is the triple decrement here actually right or is it a mistake? Because it looks like POP rr only increments the stack pointer twice, so it seems a bit weird to me that doing a PUSH followed by a POP doesn't actually restore the same SP as before.

https://github.com/Gekkio/gb-ctr/blob/master/chapter/cpu/instruction-set.tex#L713-L715

Awesome work btw, I love the timing diagrams in this manual!!