Related Issues (20)
- Failed to pass the float riscv-tests in O3CPU HOT 1
- RISC-V RVV Bad execution of VectorIntMask instruction
- Add gcc 13 to the compiler tests HOT 2
- Queued prefetcher only looks into Data TLB (DTB), which makes it inefficient with I-side prefetchers
- Support non-block prefetch inst in Ruby
- Model RVV permutation instructions more granularly
- Prefetcher coverage, accuracy calculation and throttling mechanism that requires correct pfUseful metric is incorrect for classic cache HOT 1
- Q: highly likely incorrect aarch64 ldaxrh instruction disassembly HOT 2
- Hang when simulated program's input is near INT_MIN HOT 7
- Drop support for Ubuntu 20.04 HOT 4
- Ruby recycle and stall_and_wait message delivery errors HOT 1
- The checkpoint feature may not have successfully saved and restored some data. HOT 4
- Binaries compiled on Apple Silicon (ARM) are being processed as Power ISA in SE mode HOT 3
- LoongArch porting
- How can I specify in the configuration file or command line that my simulation can wait for remote GDB connections before starting simulation HOT 4
- Fix daily tests failing due to removing gcn3_x86 HOT 7
- RISCV RVV vfredmax.vs and vfredmin.vs implementation is incorrect HOT 2
- RVV instruction vmem faults caused by incorrect vl HOT 1
- CLFLUSH causes TLB assertion error HOT 1
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