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View Code? Open in Web Editor NEW本项目的成果是在龙芯提供的 FPGA 实验平台上设计并实现基于 MIPS 32 的 CPU,并使用实验板上的周边硬件,成为一个片上系统。 不仅支持大赛要求的57 条指令以及其他复杂运算等32条指令,还完成了CP0和TLB的设计以及实现了对异常和 冲突的处理。能够运行功能、性能测试。
本项目的成果是在龙芯提供的 FPGA 实验平台上设计并实现基于 MIPS 32 的 CPU,并使用实验板上的周边硬件,成为一个片上系统。 不仅支持大赛要求的57 条指令以及其他复杂运算等32条指令,还完成了CP0和TLB的设计以及实现了对异常和 冲突的处理。能够运行功能、性能测试。
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