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3dunderworld-sls-gpu_cpu

A structured light scanner

3x3_matrix_systolic_array_multiplier

3×3脉动阵列乘法器

anavigation

单纯就是一个导航。

booth_multipliers

Parameterized Booth Multiplier in Verilog 2001

brent-kung-adder

Python code for genrating Brent Kung Adder in verilog(.v)

camkes

Component Architecture test suite and example apps.

camkes-manifest

Top level project for CAmkES, a component platform that provides support for developing and building static seL4 systems as a collection of interacting components.

camkes-tool

The main CAmkES tool

camkes-vm

Virtual Machine build as a CAmkES component.

camkes-vm-examples-manifest

capdl

dpfs

DPU-Powered File System Virtualization over virtio-fs

editor.md

The open source embeddable online markdown editor (component).

geeknav

网址导航，具备很酷的界面和完备的管理功能

isabelle

git mirror of the Munich isabelle hg repository

kernel

kernel-1

Mirror of https://gitlab.redox-os.org/redox-os/kernel

kubeasz

使用Ansible脚本安装K8S集群，介绍组件交互原理，方便直接，不受国内网络环境影响

l4v

seL4 specification and proofs

musllibc

netfpga-10g-upb-openflow

An OpenFlow implementation for the NetFPGA-10G card

open-rdma

RoCE v2 hardware implementation using Spinal HDL

prefix_adder

N bit Parallel Prefix Adder using Verilog HDL

pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

roce-sim

rtt

sel4

The seL4 microkernel

sel4bench

sel4 benchmarking applications and support library.

sel4bench-manifest

Manifest of the seL4bench project, which contains microbenchmarks for seL4.

sel4test

Test suite for seL4.