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asic-design

CAN-AHB Lite Bus Transfer Project

asic-design-1

This repository contains the source code files for an AHB to CAN interface module that was designed for Purdue's ASIC Design Lab.

asic_labs_fa21

awesome-image-registration

image registration related books, papers, videos, and toolboxes

bracucse460

VLSI Design - Spring 2022

computer-systems-ucas

**科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

computerarchitecturelab

This repository is used to release the Labs of Computer Architecture Course from USTC

cores

Various HDL (Verilog) IP Cores

course-advancedvlsi-eccdeisgn

Error Correcting Code Engine with hamming and RS

deep-learning-peak-detection

Implementation of a deep learning model for finding peaks in RPLC output

digital_ic_design_notes

数字IC设计 学习笔记

ecc_enc_dec

Encoder decoder- design, verification and synthesis project

ecc_hardware

Hardware implementation of Error-Correction Code in Verilog

eccexamples

Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material

ece5745-tut6-asic-flow

ECE 5745 Tutorial 6: Automated ASIC Flow

edac_asic_design

Synthesizable RTL of Hamming Code based Error Detection and Correction Circuit

ee260_lab

EE 260 Winter 2017: Advanced VLSI Design

error-correction-code-peripheral-accelerator

Verilog design for accelerator device capable of correcting error of received messages using matrix multiplication

error-correctioncodes

fpga

数字IC相关资料

fpga-1

FPGA

fpga-imaging-library

An open source library for image processing on FPGA.

fpgaandcnn

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

fpgaandimage

image processing based FPGA

fpgaandstudy

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

hamming-ecc

Verilog module that receives a data input on 32 bits and returns the data output on 32 bits, where the flipped bit is corrected. If there are two bit flips, then a signal will be activated stating so

hdl_ecc

hitsz-minirv-1

HITSZ 2020春 计算机设计与实践课程，实现基于 miniRV-1 的单周期和流水线CPU

interview_digital_ic

关于数字IC的笔试面试题

learn-git

Learn git