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hades-levi's Projects

nvdla icon nvdla

RTL, Cmodel, and testbench for NVDLA

oh icon oh

Verilog library for ASIC and FPGA designers

risc-v-32-cpu icon risc-v-32-cpu

risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog

risc-v-32i icon risc-v-32i

体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器

risc_cpu_8bit icon risc_cpu_8bit

参考《ASIC设计理论与实践RTL验证、综合与版图设计》实现的RISC的8位CPU,支持HLT/SKZ/ADD/AND/XOR/LDA/STO/JMP指令

shape_based_matching icon shape_based_matching

try to implement halcon shape based matching, refer to machine vision algorithms and applications, page 317 3.11.5, written by halcon engineers

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