hamsternz / displayport_verilog Goto Github PK

line103
assign preemp_level = channel_adjust[3:0];

it shoud be
assign preemp_level = channel_adjust[3:2];

I use 1485/2700 can display

line182 default: out_data[53:36] <= { in_data[53:44], in_data[44:36]};
it should be
default: out_data[53:36] <= { in_data[53:45], in_data[44:36]};

line196 default: out_data[71:54] <= { in_data[71:64], in_data[63:56] };
it should be
default: out_data[71:54] <= { in_data[71:63], in_data[62:54] };

line227 ~line285

Bit 4:3 = PRE-EMPHASIS_SET,your code set Bit 5:4 = PRE-EMPHASIS_SET

file: /test_streams/test_source_720p_RGB_444_colourbar.v
'localparam [8:0] MVID' according M calculation should be 0x033, but there's a typo 0x68 there. However it doesn't cause any issues.

When showing the 800x600 colour bars the transition between some colour transitions show unexpected artifacts that look to be one pixel wide, on the blue channel. It looks to be offset one pixel to the right.

This might be a "works as expected" with monitors image scaling, but is more likely to be an error in the test pattern.

hello ，
I am using it on my genesys2 board with GTX ,but I have some questions:
1.this project cannot work on my 4k displayer with the test source 3840*2160YCC_422_CH2
2.it cannot work with the tese_source_800_600_Ch4 since I have changed the "source_channel_count" from 3'b010 to 3'b100 because I want to use 4 channels
3.in Displayport Standard V1.2.PDF,I don't find some detailed examples or informations which describes the relationship between TU and symbol_clk or stream_clk,so I cannot understand the TUs' arrangement in your test sources

now I want to wirte a project which can support 4K 60fps display,if you can help me ,I would thank you very much