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Consider the following program (dot representation):

Components [3], then [2], then [5] can be removed because the output of [3] is not connected. This is one example. An optimizer block should remove unconnected blocks and all predecessors. The optimized output should be:

The component graph can have unconnected nodes, but the graph must be a DAG.
The scala-graph library has a module to add graph constraints. It must be used to refuse acyclic nodes or edges additions.

The dot generation has been improved a lot. For now, the graph is converted to dot using the graph-dot library, but sometimes the diagram layout is not very pretty because of the order of the components stored in the graph.

It would be nice if the components could be ordered before generating the dot file, so the final layout can be improved. But can we specify nodes order to graph-dot ? Under test...

Current (ugly) diagram:

These two examples use anonymous components declaration:

1. Same button to 2 LEDs

 val led1 = DigitalOutput(Pin('B', 5)).in
 val led2 = DigitalOutput(Pin('B', 6)).in

 DigitalInput(Pin('A', 1)).out --> led1
 DigitalInput(Pin('A', 1)).out --> led2

2. Button to the same LED

val btn1 = DigitalInput(Stm32stk.pin_btn)
btn1.out --> DigitalOutput(Pin('B', 5)).in
btn1.out --> DigitalOutput(Pin('B', 5)).in

For now, this is not supported. The code is generated, but wrong. Compilation exception. If the first example, the function pollDigitalInputA1 is declared twice (because two buttons are created for the same pin).

Excepted results:

• For the first example, only one input component should be created.
• For the second, a PortInputShortCircuit exception should be thrown.

If this work, this would be a great enhancement.

For now, warnings for unconnected components and ports looks like this:

WARN: 1 component(s) declared but not connected at all:
    - Cmp[3] 'digital output on pin 42'

WARN: 1 unconnected port(s) found:
    - InputPort[1] of Cmp[3] 'digital output on pin 42'

In fact, the component Cmp[3] is the output val led4 = DigitalOutput(42). The instance name of the component (or the port) should be printed in the warning.
To do this, the "new" Reflection API for Scala must be used, but it is not so trivial to get this information from the AST at runtime.
http://stackoverflow.com/questions/26421725/instance-name-at-runtime-with-the-scala-reflection-api
http://stackoverflow.com/questions/744226/java-reflection-how-to-get-the-name-of-a-variable

Ports class definitions are the following:

abstract class Port[+T <: CType : TypeTag](owner: Component)
abstract class InputPort[+T <: CType : TypeTag](owner: Component) extends Port[T](owner)
abstract class OutputPort[+T <: CType : TypeTag](owner: Component) extends Port[T](owner)

The type T is used only in covariant positions. All subclasses of the abstract class CType can be used with ports.

The following code will compile (because of variance), but an exception will be thrown at runtime only:

val led1 = DigitalOutput(Stm32stk.pin_led)
val cst1 = Constant(uint8(128))
cst1.out --> led1.in // Wants to connect uint8 --> bool

This is the generated exception when ports are connected:

Ports types mismatch. Connection error !
Cannot connect the output `out` (type `uint8`) of Cmp[1] 'Constant'
to the input `in` (type `bool`) of Cmp[3] 'DigitalOutput'.

This should be generated at compilation time.

The following application compute math operations from constant values:

For now, these math operations are computed on each loop iterations, but it is not necessary.

while(1) {
    // 1) Read inputs

    // 2) Loop logic
    uint16_t out_cmp10 = 4096 / 2;
    uint16_t out_cmp11 = 4096 / 8;
    uint16_t out_cmp12 = out_cmp10 - 2044;
    uint16_t out_cmp13 = out_cmp11 + 512;
    uint16_t out_cmp14 = 512 * out_cmp12;

    // 3) Update outputs
    out_cmp02.set(true);
    out_cmp03.setPeriod(out_cmp13);
    out_cmp04.setPeriod(out_cmp14);
}

Constant should be "propagated" on the init. This would be a great improvement !

Define a fixed loop cycle (or a multiple of it) to be deterministic. = PLC ?

Add an helper class to create basic components using small part of C code.

The user can declare global variables and define the while loop code using C directly in the Scala DSL.
Can be dangerous, the C code is not checked (just pasted). It sould compile and be fast enough to not block the code execution.

An exception must be thrown if the same input or output is used twice (or many), with different configuration.
For instance, if an output is used as digital and PWM output in the same program. The output is stored only once in the graph, but a Cast exception will be thrown for now..

Find a demo application with the current available components to illustrate the toolchain, from the DSL program to the simulation and chronogram.

Once components are instantiated, they are automatically added as node in the graph. Then, they can be connected with ports.
For now, the user cannot disconnect a port or remove a component. Maybe in the furutre...

Consider this simple program:

val cst1 = Constant(bool(v = true))
val led1 = DigitalOutput(Stm32stk.pin_led)

cst1.out --> led1.in
cst1.out --> led1.in // Short circuit or not ?

Is this program valid or not ?
1. No: short circuit detected.

[ERROR] ContextLogger - Short circuit !
The input 'in' of Cmp[2] 'DigitalOutput' is already connected.

2. Yes: ignore the second connection if components ID are the same.

We are not in VHDL (= priority of the last affectation), so IMHO an exception should be thrown. Electrically it is possible but seams a bit strange in the code.
@pmudry What do you think, answer 1, 2, other ? Thanks

Add boolean operators as syntactic sugar to create components (logic gates).
Current version:

// OA = AB + BC + AC
val andA1 = And2(A, B).out
val andA2 = And2(B, C).out
val andA3 = And2(A, C).out
Or3(andA1, andA3, andA2).out --> OA

Should be something like:

val andA1 = (A & B).out