hitomi2500 / wasca Goto Github PK

Long time no see ! Pseudo Saturn Kai development reached a milestone big enough so that I can finally put more time on Wasca development.

And, as indicated in the title, I'm currently experiencing SDRAM access issues in firmware v1.x (MAX 10-based) from a design to another, which improves by randomly changing settings in Qsys and heavy prayings ... in simpler words, I'm flooded with technical difficulty of firmware development.

So I would like to know how you managed to adjust access timing for SDRAM in v1.0 board (which was running Saturn test utility from emulated boot ROM, hence with working SDRAM access) : from my limited understanding, as this requires to dedicate one clock signal for SDRAM chip (and adjust its phase with slack from address/data signals), I was thinking to use second clock output from MAX10's PLL as clock signal for SDRAM.
But firmware v1.0/v1.1 uses only one clock output from PLL, so if there's another way to adjust SDRAM access timing, please inform me about it.

I suppose you still prefer the snickerdoodle-based architecture, but that would be really appreciated if you want to give an hand on MAX 10 one ♪