100daysofrtl

100 Days of RTL

256-point_parallel_fft_dif

32bit_2_24bit_float_unsigned_conv

32by16-rgb-panel-control-with-zynq

Driving 32BY16 RGB Panel using ZYNQ SoC

5-stage-pipeline-risc-v-architecture-in-verilog

This repository contains the verilog cde files of 5 stage Pipeline RISC-V architecture

a2-hls-mpsoc

Heterogenous Architecture for Big Data Algorithms

academicpages.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

adapt_workshop_vai101

ai-chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

ai_edge_contest

For the 2nd AI Edge Contest(https://signate.jp/competitions/191)

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.

alveo-pynq

Introductory examples for using PYNQ with Alveo

alveo_training_materials

Alveo Training Material

anbox-arm64

Anbox is a container-based approach to boot a full Android system on a regular GNU/Linux system

andrew-ng-notes

This is Andrew NG Coursera Handwritten Notes.

assignment2

For ECE1373 Assignment 2 Submission

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asyncnoc-2011

Automatically exported from code.google.com/p/asyncnoc-2011

audio-transmission-and-reception-over-rf

RF transmission and reception link for audio application

auto_bus

This tool generate bus (in Verilog) and top level logic automatically.

awesome-cheatsheets

👩‍💻👨‍💻 Awesome cheatsheets for popular programming languages, frameworks and development tools. They include everything you should know in one single file.

awesome-plonk

A curated list of awesome things related to plonk proof system

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi-pcie-core

axi-pcie-core

axi4_master

Custom axi4 master

ba_ps-pl-communication

bachelor thesis about PS-PL Communication on a SoC. Working on the MicroZed-Board with Vivado and PetaLinux.

bachelor_hardware

Hardware for mnist-classification

barvinn

BARVINN: A Barrel RISC-V Neural Network Accelerator

bedrock

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

beehive-a-many-core-computer-for-fpgas