hossamfadeel / barvinn

BARVINN: A Barrel RISC-V Neural Network Accelerator

Hi there 👋

• 🔭 I’m currently working on designing and implementing digital circuits for FPGA and ASIC systems...
• 🌱 I’m currently learning about the latest advances in computing hardware and algorithmic research...
• 👯 I’m looking to collaborate on projects that leverage the power of FPGA and high-speed communication interfaces and protocols to create efficient and reliable systems...
• 💬 Ask me about my experience with ASIC tape-outs, RTL coding, FPGA synthesis, or anything related to hardware architecture and design!...
• 📫 How to reach me: Github, Linkedin

Hey 👋, I'm Hossam Hassan!

Glad to see you here!  

Skills

Programming Languages:

• Verilog
• SystemVerilog
• VHDL
• Python
• C
• Tcl
• Bash

Hardware Platforms:

• FPGAs
  • Xilinx FPGAs
  • Intel FPGAs
• Accelerators cards
  • Xilinx Accelerators cards (U55, U280, U250)
  • Intel Accelerators cards (BittWare IA-840f)
• Microcontroller
  • STM32 Microcontroller
  • Arduino
  • PIC
  • Cypress PSoC
• Microprocessors
  • ARM
  • RISC-V
• ASICs
  • MagnaChip 130nm
  • Samsung 65nm

Software and Tools:

• Xilinx (Vitis HLS, Vivado, Vitis)
• Intel (Quartus Prime, oneAPI)
• MATLAB
• Synopsys: Design Compiler, VCS, IC Compiler.
• Cadence: Genus, Xcelium
• Mentor Graphics ModelSim/Questa

Protocols:

• AXI-4 MM, Lite, and Stream protocol
• ABP bus protocol
• PCIe interface

Other Skills and Technologies:

• High-Level Synthesis (HLS) flow
• High-speed communication protocols
• Zero-Knowledge Proof (ZKP) related technology
• Hardware Implementation of SHA-256 algorithm
• Hardware Development of the Number Theoretic Transform (NTT)
• Hardware Development of the Multi-Scalar Multiplication (MSM)
• Hardware Development of FPGA-based Underwater Sonar Devices
• Implementing Lossless and Near-Lossless Sonar audio and RAW Data compression using IMA ADPCM Algorithm
• Implementing a modified version JPEG-LS (JPEG- Lossless image compression standard)
• FPGA-to-FPGA Communication Using Xilinx Aurora IP
• Ethernet-Based data transfer between PC Software and FPGA-Based Sonar Hardware Device using LWIP
• Custom USB HID implementation
• Debugging and redesigning a VHDL code for variable frequency generation and control of the Sonar Acoustic Camera Device based on Xilinx Artix-7 FPGA
• MATLAB for various tasks, including verification of I2S protocol and FFT output comparison
• RTL design and verification of various digital circuits and systems
• FPGA and GPU acceleration for ZKP systems

Talking about Personal Stuffs:

• 👨🏻‍💻   Most of my projects are available on Github.
• 📫   How to reach me: [email protected].

My Absolute Favorites:

• 💻   I love exploring new tech stack and building cool stuffs.

• 📰   Reading & writing tech blogs whenever possible.

• 🍕   Hackathons, meetups & tech events.

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