afu_driver/verilog/top.vq error about pslse

[umarajag]

Hi,
On the testbench we have a breakpoint signal declared as an output. Hence the declaration
module top (
output breakpoint
);
on lines numbers 19, 20, 21

[lemon34]

But when i simulate top.v in vivado , pop-up error syntax error，when i delete the ");", it simulate succefully

[umarajag]

Hi,
I tried a fresh pull from gitHub of the code and tried a Vivado sim. It worked without any edits on the top.v (I tried the demo memcpy model to simulate this)

Can you please check whether there has been some inadvertent edits on the top.v (other than the ones you had specifically put) to get your model to simulate?

[umarajag]

Hi,
Please ensure that you are following the steps given in the README and QUICK_START documents in the pslse checkout directory
While compiling the top.v please remember to give the -svlog switch (on the xvlog command), and for xelab command, we should have the -sv_lib libdpi -sv_root $ options, before simulating

[umarajag]

Hi,
xelab -timescale 1ns/1ps -svlog $TOP/top.v -sv_root $ROOT_DIR -sv_lib libdpi -debug all

Here is the command to run xelab
where in the $ROOT_DIR should have the libdpi.so or a link to that file

[umarajag]

Question: do i need a testbench in Vivado Simulator?

Answer; the $TOP/top.v mentioned in the xelab command should be the testbench. On the pslse directory in the github, you could find the testbench at pslse/afu_driver/verilog/top.v
You will have to instantiate the afu you have designed on the testbench to simulate it with the pslse