ibug / cod-2019

Computer Organization and Design course of 2019

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cod-2019's Issues

VGA.v似乎存在问题

这个always块里对变量vc的处理似乎有问题：
`
always @(posedge clk) begin

    if (rst) begin

        hc <= 0;

        vc <= 0;

    end else if (ce) begin

        if (hc >= HD + HF + HS + HB - 1)

            hc <= 0;

        else begin

            hc <= hc + 1;

            if (vc >= VD + VF + VS + VB - 1)

                vc <= 0;

            else

                vc <= vc + 1;

        end

    end

end`

从这个代码我理解出的意思，是每次clk上升沿触发时，若满足条件使hc加1，则vc未到最大值时也会加1。但vc应该在hs低电平信号后才加1，也就是至少hc达到HD+HF+HS（即扫描完一行同步）后才会加1。
我的想法是这样的：
`
always @(posedge clk,posedge rst) begin

    if (rst) begin

        hc <= 0;

    end else if (ce) begin

        if (hc >= HD + HF + HS + HB - 1)

            hc <= 0;

        else begin

            hc <= hc + 1;

        end

    end

end

always @(posedge hs,posedge rst) begin

    if (rst) begin

        vc <= 0;

    end else if (ce) begin

        if (vc >= VD + VF + VS + VB - 1)

            vc <= 0;

        else begin

            vc <= vc + 1;

        end

    end

end

`