idea-fasoc / fasoc

FASoC: Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits

The FASoC Program is focused on developing a complete system-on-chip (SoC) synthesis tool from user specification to GDSII. See more on our website.

FASoC tool can be operated in three modes, "Verilog", "Macro" and "Full" modes.

Verilog Generation Mode

The provided generators can generate fully synthesizable verilog products using the user input specification file. The generated verilog will be derived from pre-characterized modules. Future releases of the tool will also generate a human readable constraint guidance that will aid in maximizing post layout design performance.

Macro/Full Generation Mode

The macro generation mode will generate hard macros in addition to the verilog. These hard macros are synthesized and implemented versions of the verilog output using recommended constraints and physical guidance. This mode will require the commercial tools, access to the standard/cells, PDK and other tools. It will also require an automated flow (cadre flow) as well as several private files that are restricted due to NDA requirements.

Setup instructions

1. Tool requirements:

   • General: Python 3.6/3.7 (packages getopt, math, numpy, os, re, shutil, subprocess, sys, smtplib, datetime, logging, matplotlib). Python versions below 3.6 are not supported.
   • Cadre Flow:
     • Synopsys Library Compiler (2018.06)
     • Synopsys Design Compiler (2018.06) (Cadence Genus v18.10 can also be used for LDO-GEN & PLL-GEN)
     • Quantus QRC extraction (15.23.000)
     • Cadence Innovus (v18.10)
     • Synopsys Primetime (2018.06)
     • Mentor Graphics Calibre (2019.3_25)
   • Synopsys HSPICE (2017.03-SP1)
   • Cadence Liberate (16.1.1.132)
   • Cadence Spectre (15.1.0)

   Newer versions of the tools are expected, but not guaranteed to work.

2. Run the environment checker script to ensure all the tools are setup

   make check_env

3. Ensure you have access to the required private repository for FASoC. Please contact [email protected] if you need access

4. Ensure you have ssh keys setup for github. Instructions for generating and adding ssh keys can be found here.

5. Clone the FASoC repository

   git clone [email protected]:idea-fasoc/fasoc.git

6. Initialize the submodules

   cd fasoc
   git submodule update --init --recursive

7. Setup the cadre flow to for your specific location. The "Macro/Full" modes currently requires TSMC65LP PDK and ARM standard cells. More instructions on how to setup this particular platform can be found in the Cadre Flow Guide

8. Change directory to the generator of interest and follow instructions in the readme

Citation

If you find this tool useful in your research, we kindly request to cite our paper:

• T. Ajayi et al., “An open-source framework for autonomous soc design with analog block generation,” in 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC). IEEE, 2020.

• @inproceedings{ajayi2020open,
  title={An open-source framework for autonomous SoC design with analog block generation},
  author={Ajayi, Tutu and Kamineni, Sumanth and Cherivirala, Yaswanth K and Fayazi, Morteza and Kwon, Kyumin and Saligane, Mehdi and Gupta, Shourya and Chen, Chien-Hen and Sylvester, Dennis and Blaauw, David and others},
  booktitle={2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)},
  pages={141--146},
  year={2020},
  organization={IEEE}}

fasoc's Issues

Naming Discrepancy Between GF180MCU OpenPDK Releases

Description

In the earlier releases of the PDK (e.g. 3af133706e554a740cfe60f21e773d9eaa41838c), the naming conventions are kept the same with the commercial release. However, in newer releases the names are modified to be consistent with the previous SKY130 OpenPDK.

Investigation

In release 3af133706e554a740cfe60f21e773d9eaa41838c (2022-11-08)

The names are consistent with that in the commercial PDK release

MOS transistors are: nmos_3p3, pmos_6p0, …
Metal Names are: Metal1, Metal2, …

In newer OpenPDK releases:

MOS transistors are: nfet_03v3, pfet_06v0
Metal Names are: M1, M2, …

Issue

This discrepancy causes some issue when tools from different worlds are used together:

• LVS is problematic because the name differences. The transistor names need to be modified manually.
• The OpenLane Docker image released with GFMPW-0 is nolonger working. I used the older version of the PDK to do digital synthesis.

Link

google doc

dcdc_gen

Is it some issue in the folder create part, as it will not create the simulation folder by itself

LDO_gen full mode issue

I was using calibre/2019.3_25 when "make gen_12lp_full" but it didn't generate ldo.pex.netlist which cause the post pex simulation not working. I changed to calibre/2020.3_38.22_aoj and solved the issue.

LDO-GEN verilog mode doesn't work when the repo folder "verilog" is chosen as output directory

temp_sensor_gen incorrect file name

Hi, please take a look at the src folder, I think it is just a mismatch between the python and the folder files

PLL_gen probelm

There is no script folder from the github private view.

Memory_gen folder not found

For memory_gen, running the macro mode, it is unable to find this folder. Please take a look

check_env.py small bugs

There are some small bugs on the check_env, I am getting errors for checking python version and other cadence tools. And there should be some check for the python libraries like numpy and so on. So just have that updated.

cdc_gen hspice not found

I have checked the private folder, and there is no hspice there, is that some linkage problem

how to access private?

May I access private/cad?

adc_gen cell cannot find problem

When I run adc_gen tsmc65lp macro mode, and this is some error, and I have checked the folder, I have also attached the result in the picture

Documentation on current set of generators

You seem to have a whole bunch of generators at https://github.com/idea-fasoc/fasoc/tree/master/generators but very little documentation on what the generators do, how types of ranges they work on, how they are used, etc.

Might be a good idea to add a top level README.md to the generators directory and then a bit more information to each of the generators README files.

ldo_gen file not found

Using lower case

Based on what we have discussed, we will use the lower case letters for our final outputs.
Memory:
So, would you please change "Power" to "power" and AspectRatio to "aspect_ratio" in the mem-gen output json file?
PLL:
would you please change "Fnom_min" to "fnom_min", "Fnom_max" to "Fnom_max" and "aspect ratio" to "aspect_ratio" in the pll-gen output json file?

correct-by-construction never defined?

The page @ https://fasoc.engin.umich.edu/ says;

automatically synthesize “correct-by-construction” Verilog descriptions

There doesn't seem to be any definition about what you mean by “correct-by-construction” nor how your guarantee that result? Since it seems to be a core principle, I would have expected it to be clearly described + defined somewhere?

submodule update error after having access to all repos

I have pull a new folder and runs the following command, also, I have access to all repos. And I am get this error, please take a look

Readme requirements unclear?

The README file says the following;

Requirements: Python 3.6/3.7 (packages getopt, math, numpy, os, re, shutil, subprocess, sys, smtplib, datetime, logging, matplotlib). Python 3 is not supported.

I assume that last sentence should be Python 2 is not supported?

platform extension

As I am currently struggling to update config files and generate new Aux-cell using other PDKs, I was wondering if the source of the "AUXCELL_GEN" tool is available somewhere.

Further, I was wondering how could I extend the platform from tsmc65lp to my own PDKs(like tsmc130). And I would appreciate any help.
Best regards.

Is it possible to replace closed source tools with open source equivalents?

There is lot of information about potentially alternative flows in a doc at http://j.mp/openeda-diagram

The OpenRoad Project seems like it would also be a potentially good option.

Remove "This is the readme" from top of README files

A lot of the README files seem to have a "This is the readme" at the top of them. IE https://github.com/idea-fasoc/fasoc/tree/master/generators/adc-gen

The title should be the second line.