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Tetris created in SystemVerilog

Tcl 0.12% Verilog 9.38% Makefile 0.02% C 2.59% SystemVerilog 0.29% VHDL 86.72% C++ 0.36% Pascal 0.01% Shell 0.15% Stata 0.02% Forth 0.01% Batchfile 0.01% PureBasic 0.01% SuperCollider 0.07% Assembly 0.26% CMake 0.01% CartoCSS 0.01%

tetris's Introduction

Project Overview

This repository contains an implementation of Tetris entirely in SystemVerilog written by Jacob Poeschel and Meredith Naylor. The project was designed with the support of both Vivado and Vitis.

Source code for the Vivado IPs which were used in this project can be found in the "ip_repo" folder.

All source code can be found in the "tetris_project/ece385_final_project.srcs" at this path: 'tetris_project/ece385_final_project.srcs/sources_1/new'. To read about the technical details of this project, please download "TetrisReport".

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