jameslzhu / riscv-card Goto Github PK

Is this pseudo Code right (rd=M[rs1]+imm) or rather rd=M[rs1+imm] ?

I believe the fence instruction is missing from RV32I. Only fence.i was evicted from RV32I and sent as a loner to the Zifencei extension.

Is this note correct? I believe the immediate field is sign extended (not zero extended) and then is treated (along with rs1) as an unsigned value for the comparison.

See RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, December 13, 2019. Page 18:

"SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
XLEN bits then treated as an unsigned number)."

@esmil The Notes column, the first two "zero-extends" comments are mis-placed. They should be beside the Logical Shift Right commands, not the Set Less Than instructions. @

See pp 15-16 of https://content.riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf . JALR adds imm[11:0] (sign-extended) and rs1 to generate new PC.

Is this note correct? Both source operands are registers. What is being zero-extended? The < comparison is treating both operands as unsigned but nothing is being sign-extended or zero-extended.

The text in "Shift Right Arith*" has an asterisk with no apparent purpose.

Is this project still mataining?

If so, it would be great to have some content about RISC-V64 instructions and CSR registers.

Thanks.

The branch greater equal (bge) instruction is with the '≤' sign instead of '≥'

You are missing at least the C.FLW, C.FLD, C.FSW, C.FSD instructions.

Per ISA spec:

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
..
The FNMSUB and FNMADD instructions are counterintuitively named, owing to the naming
of the corresponding instructions in MIPS-IV.

Could you add a compiled version (PDF)? I don't have a TEX compiler up and running, but would be great to see the sheet.

Two mnemonic in RV23M seem mispelled:

• "mulu" should be "mulhu"
• "mulsu" should be "mulhsu"