jbrzusto / digdar Goto Github PK

ARP is not always detected, and not always at same location, so:

• treat the ACP count as the azimuth clock
• track running mean and variance of the ACP (including fractional portion) at which ARP is detected

FPGA TODO:

• new SWEEP_COUNTER uint32 records number of times ACP count has wrapped past a specified value (e.g. 450 for Furuno, 4096 for Bridgemaster E)
• when SWEEP_COUNTER increments, record:
  • ADC clocks since reset
  • ARP count
  • ADC clocks since last ARP
• when TRIG is detected, record:
  • ACP count
  • ADC clocks since last ACP reset

jbrzusto/ogdar will use zero as a sentinel value indicating "not a sample" to recognize metadata or uninitialized regions in the sample buffer.

Something is wrong in the logic for setting metadata registers.
In Vivado 2013.3, critical logic is trimmed (with warning 8232) if any registers are
set from red_pitaya_digdar.v in a clause like

always @(posedge adc_clk_i) begin
   if (adc_rstn_i == 1'b0) begin
       trig_count <= 32'h0;
   end
end

For now, we're working around this by having Init() from jbrzusto/ogdar/fpga/fpga.go
set initial values.

• it's fake and confusing. The samples to the left of t=0 are later in time, not earlier, because trigger detection is what starts filling the buffer in our FPGA build.

These are signed but apparently being plotted as unsigned, or something like that, because
the display saturates at both ends.