jimtwotiger / alldigitalradio

All Digital Radio Platform written in nmigen targeting FPGAs (for now)

A toolbox for creating entirely digital radios using nmigen.

This is a collection of functional components used to build digital radios that use direct RF sampling at one bit of precision using SERDES transceivers on FPGAs. It was initially broken out of the onebitbt repository so that components could be reused in other kinds of radios (i.e. low-speed WiFi). it is far from perfect and is expected to evolve fairly quickly. If you want to use it, I'd suggest forking it so that you aren't caught off guard when an interface changes.

Getting started.

First, install dependencies (ideally in a python3 virtual environment)

pip install numpy scipy jupyterlab matplotlib
pip install git+https://github.com/nmigen/nmigen

Pro-tip: if you want to hack on this repository, I'd recomment cloning it and then doing:

pip install -e [path to checkout]

This will allow you to depend on this package from another project and edit this package live without needing to reinstall.

Next (if you have the same TE0714 hardware as I) you can run simple examples like:

python -m alldigitalradio.examples.cw_out te0714 # Transmits a 2.5Ghz constant wave on the SERDES TX
python -m alldigitalradio.examples.loopback te0714 # Transmits whatever is received back out.

Documentation / How To

For the various building blocks, you can refer to the notebooks in the research directory.

• Downconversion - Conversion from a carrier-modulated signal to baseband (with 1-bit signals)
• Filtering - Comically simple filtering.
• Synchronization - Symbol synchronization.
• Trigonometry - Computing the magnitude of a complext signal.
• Shift Registers - Shift registers underpinning whitening and CRC checking.
• Parsing - Not nmigen, but just generic Python utilities to parse and generate arbitrary packets.

FAQ

Something is incorrect!

Please let me know! Twitter (@newhouseb) or GitHub is fine. I've been engineering in a cave and have no professional experience in this space, so I'm sure there are errors in addition to random bugs.

Credits

The Xilinx SERDES implemenation is derived from the migen implementation in liteiclink.