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fmh_gpib_core is a GPIB IP core written in VHDL.  Currently, a
frontend with a cb7210.2 style register interface has been implemented
(see src/frontends/frontend_cb7210p2.vhd).
It supports IEEE 488.1 subsets SH1, AH1, T5, TE5, L3, LE3, SR1,
RL1, PP0-PP2, DC1, DT1, and C1-C5.

See src/example/gpib_top.vhd for an example of how the cb7210.2-style
frontend might be connected to a ARM PL330 dma controller and
a digital filter for the GPIB control lines.

The underlying GPIB logic is separated from the register interface 
so that multiple front end register layouts may be implemented on top
of the common core.

The latest version of this IP core may be found at:

https://github.com/fmhess/fmh_gpib_core

This package is copyright Frank Mori Hess 2017, all rights reserved.
If you wish to obtain a license to use this IP core, contact the author:
Frank Mori Hess [email protected] .