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Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

Home Page: https://jn513.github.io/Risco-5/

License: CERN Open Hardware Licence Version 2 - Permissive

Verilog 47.36% Tcl 30.44% Makefile 2.51% Shell 1.10% C 1.44% Assembly 16.90% SystemVerilog 0.24%
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

risco-5's Introduction

About Me

Hello, my name is Julio Nunes Avelar, a Brazilian maker since I can remember. I have a degree in Information Technology and I am currently a Computer Engineering student at the State University of Campinas (UNICAMP).

I am a huge hardware enthusiast and love developing new things. I am part of UNICAMP's study and development group for embedded systems (Embarcações). In my spare time, I maintain a technology blog called Bzóide, contribute to open-source projects, and work on some random projects, many of which are openly available on this GitHub.

Areas of Interest

  • Embedded Systems
  • Computer Architecture
  • RISC-V
  • Real-Time Operating Systems (RTOS)
  • Open Source Hardware and Free Software
  • Operating Systems

Contact

My GitHub Stats:

JN513's GitHub stats

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risco-5's People

Contributors

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Watchers

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Forkers

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risco-5's Issues

Concertar temporizacão da UART

provavelmente o buffer circular está sofrendo overflow e a uart está dando response == 1 mesmo quando o buffer está cheio e a escrita não e possivel

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