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License: MIT License
high performance AES implementations optimized for cortex-m microcontrollers
License: MIT License
Hi,
do you plan to add the an implementation using T-tables for the CM0 target?
Thanks!
with risc-v implementations it's no longer cortexm
Hello
I'm experimenting with the STM32L151 Cortex M3 (STM32CubeIDE, GNU Tools for STM32 (9-2020-q2-update))
I have decoder
aes::mode::CBC<256, aes::target::CM3_1T_deconly, aes::mode::target::CBC_GENERIC> tcbc;
and decoding result is always wrong.
Also try CM3_1T, CM3_1T_unrolled, CM3_1T_unrolled_deconly and so on and have no luck.
(unrolled versions prodece Hard Falult on CM3_1T_unrolled_dec_round)
As soon as I switch to
aes::mode::CBC<256, aes::target::CM0_FASTMULsBOX, aes::mode::target::CBC_GENERIC> tcbc;
or
aes::mode::CBC<256, aes::target::CM0_sBOX, aes::mode::target::CBC_GENERIC> tcbc;
The decoding is going great.
What am I doing wrong?
otherwise no padding, will read and write past the in/out buffers
Hi,
do you plan to add the KeySchedule for the decryption also for the CM0 target?
Thanks!
If true, then the last compressed processing instruction can leak secret data.
ctx, input and output data need to be 4 byte aligned to not crash
cm0 will crash even with unaligned ldr
cm7 prefers 8 byte alignment for perf reasons
otherwise no padding/discarding, will read and write past the in/out buffers
Hey, this library looks awesome! Just curious if this can be used for AES-GCM ?
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