jracevedob Goto Github PK

followers: 11.0 following: 86.0 repos: 90.0 gists: 0.0

Name: Javier Acevedo

Type: User

Company: @Rohde-Schwarz

Twitter: enkontexter

Location: Berlin, Germany

Blog: jracevedob.github.io

Javier Acevedo

I am professional baseband system engineer in Dresden, Germany. I am mostly interested on designing and deploying versatile and agile state-of-the-art compute platforms for wireless communication systems. I am currently working on bringing hardware acceleration to the Radio Access Network (RAN), while integrating it with the Core Network.

Motto

It is better to die on your feet that live on your knees - Emiliano Zapata.

Main functional motivation

Hardware-Software Co-Design of the entire product development life cycle for 5G's RAN and Core Network.

Contact

You can contact me mainly via E-mail under the following address or Twitter account.

Current projects

In this moement, we are working on two different projects about wireless communications and genetics.

Hardware accelerated version of the Open RAN Intelligent Controller (RIC).
Hardware accelerated version of the training sequence for protein folding. ESM Meta

Javier Acevedo's Projects

ricci

This repository contains the source code for the RICCI project. RICCI represents a new and revolutionary way of understanding fashion and its role as a social driving force. By introducing automatic robot teaching concepts instead of antiquate and inconvenient robot programming, we pretend to set a new forms of human machine interactions.

risc-ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

risc-ariane

Ariane is a 6-stage RISC-V CPU

riscv-code-size-reduction

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-devops

This repository presents the implementation of communication kernels for 5G New Radio and its build and test automation, using CICD

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-llvm

SiFive's LLVM working tree

rlnc_mpsoc

This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.

ros-automatic-code-gen

In this repository, you will find the source code for generation of hardware accelerators on-the-fly for ROS nodes

rust

Empowering everyone to build reliable and efficient software.

rust-vmm-container

Container with all dependencies required for running rust-vmm crates integration tests.

scripting

In this repository, you will find different examples of shell-based scripting to execute different task ranging from automatic code generation for MPSoC to web browser manipulation.

serverless-benchmarks

SeBS: serverless benchmarking suite for automatic performance analysis of FaaS platforms.

sionna

Sionna: An Open-Source Library for Next-Generation Physical Layer Research

sympy

A computer algebra system written in pure Python

thefifthdriverai

The Fifth Driver is a project for the Adaptative Computing Developer Contest for Xilinx. We pretend to demonstrate that the Xilinx Ultrascale+ MPSoC architecture is suitable for developing machine learning applications applied to Autonomous Driving.