- ๐ Hi, Iโm Json Lee.
- ๐ Iโm interested in everything on the underlying infrastructures, including but not limited to Compiler, Programming Language, Operating System, Runtime, Computer Architecture and etc.
- ๐ซ How to reach me @lijiansong
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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.