junyang0412 / realprobe

RealProbe🔍

In-FPGA profiling tool for HLS designs

About

RealProbe is a fully-automated profiling tool to extract on-FPGA performance. With just one line---#pragma HLS RealProbe---our tool automatically generates all the code necessary to profile the exact cycle counts of an entire function hierarchy on-board. It is developed and maintained by Jiho Kim from Sharc Lab at Georgia Tech.

Useful Links

Docs: RealProbe Tutorial: (FCCM 2024)

Requirements

RealProbe expects AMD/Xilinx Vitis HLS (a part of the Vitis Unified Software Platform) and Vivado to be present on the machine it is running on. This includes setting up the environment, as described in the Vitis HLS documentation, and setting up the environment, as described in the Vivado documentation.

For FPGA board, we expect the board to support PYNQ framework.

Other than that, RealProbe is fully integrated into Vitis HLS and Vivado toolchain, requiring no additional environment settings or tool installations.

All testing has been performed using Vitis HLS 2023.1 and Vivado 2023.1, though we expect any version with an HLS LLVM frontend release.

Usage

git clone https://github.com/sharc-lab/RealProbe.git
cd RealProbe

Warning

Please note that the name of the tcl script should be hls.tcl, and don't change the variable name inside. For more information, refer examples folder for tcl script examples.

In your Makefile, specify the path to your git repository

REALPROBE_PATH := <YOUR/GIT/CLONED/PATH>/realprobe
HLS_BUILD_PATH := <YOUR/GIT/CLONED/PATH>/hls-build

Go to your project folder (with C/C++ codes and Vitis_HLS run tcl script) and copy the Makefile from RealProbe.

cp RealProbe/realprobe/Makefile .

Then, run RealProbe!

make realprobe