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This project forked from enjoy-digital/litex_vexriscv_smp_test

0.0 1.0 0.0 11.13 MB

Test with LiteX and VexRiscv SMP

Python 0.18% Verilog 99.80% Assembly 0.01% C 0.01% Shell 0.01% Makefile 0.01%

litex_vexriscv_smp's Introduction

[> Getting started
------------------
1. Install LiteX: https://github.com/enjoy-digital/litex/wiki/Installation

2. Run the simulation:
  ./sim.py  --cpu-variant 4c (suported: 1c, 2c, 4c, 8c)
  add --sdram-init to load the images
  add --trace to enable waveform that will be located in build/sim/gateware/sim.vcd

3. Test on Hardware (Arty A7 or Nexys Video):
  ./target.py --cpu-variant (suported: 1c, 2c, 4c, 8c) --uart-baudrate=1000000 --build --load
  lxterm --images=images.json /dev/ttyUSBX --speed=1000000 --no-crc

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