Contains MUX8_to_1 and DFF Verilog HDL files, alongwith their respective testbenches, compiled vvp files, and output vcd files.
Contains final Moore FSM in file named System.v alongwith it's Testbench, compiled vvp file, and output vcd file.
Contains Problem Set, and Project Report.
MUX8_to_1 modelled according to Texas Instruments 74LS253, similarly, DFF modelled according to Texas Instruments 74LS74.