A Chisel3 package to describe verilog FPGA template and macro for hardened FPGA modules
To install it, clone it then publish local:
$ git clone https://github.com/Martoni/fpgamacro.git
$ cd fpgamacro
$ sbt publishLocal
Then add these lines in your build.sbt
project :
//publish local https://github.com/Martoni/fpgamacro.git
libraryDependencies ++= Seq("org.armadeus" %% "fpgamacro" % "0.2.2")
Generating a reset pulse with initial 0 state.
Instantiation of n-bits tri-state buffers. Each lines could have common (TriStateBuffer
) or different (TristateBufferAtomic
) directions.
A PLL instanciation of MachXO3 to reverse clock (180° phase).
Some primitives blackboxed instanciation :
OSC
: internal oscillator blackboxGowin_OSC
: internal oscillator with FREQ_DIV parameterPLLVR
: Some PLL instanciation for TMDS and HyperRamRPLL
: PLL instanciation mainly for GW1NR-9CLKDIV
: clock divider (by 5 default)TMDS_PLLVR
: PLL block generated by gowin ide to drive TMDS blocksOSER10
: 10:1 serializer with friendler module namedOser10Module