kevinpinto98 Goto Github PK

100_days_of_rtl

100 days RTL challenge

advanced-physical-design-using-openlane-sky130

analog_cmos_design_i

awesome-meta-learning

A curated list of Meta Learning papers, code, books, blogs, videos, datasets and other resources.

awesome-quantum-computing

A curated list of awesome quantum computing learning and developing resources.

cirq

A python framework for creating, editing, and invoking Noisy Intermediate Scale Quantum (NISQ) circuits.

digital_vlsi_soc

hardware_ai_accelerator

introduction-to-computer-architecture-education-kit

Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

lf-building-a-risc-v-cpu-core

mips_processor

ml_for_ee

openpiton

The OpenPiton Platform

qiskit

Qiskit is an open-source SDK for working with quantum computers at the level of circuits, algorithms, and application modules.

qiskit-tutorials

A collection of Jupyter notebooks showing how to use the Qiskit SDK

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

riscv_myth_workshop

riscv_myth_workshop_may22-kevinpinto98 created by GitHub Classroom

rtl-design-with-verilog-using-sky130-technology

simplecpu

An open source CPU design and verification platform for academia

sky130rtldesignandsynthesisworkshop

sv-tutorial

SystemVerilog Tutorial

tlv_flow_lib

Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

verigpu

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

verinoc

vsd_tcl_workshop

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

vsdopen2020_tlv_risc-v_tutorial

For students of the VSDOpen2020 TL-Verilog RISC-V Tutorial