This repository documents my journey of 100 days for learning System Verilog and UVM. I was inspired to take up this challenge after reading a linkedin post by Rahul Behl.
Update: Will be taking a break from 12/12/2022 to 22/12/2022 since I need to shift my focus on my academics due to looming assignment deadlines.
- Day 1: Multiplexer
- Day 2: D Flip-flop
- Day 3: Edge Detector
- Day 4: 4-bit Counter
- Day 5: Finite State Machine
- Day 6: Clock Divide-by-3
- Day 7: Shift Register
- Day 8: Binary-to-Gray Converter
- Day 9: Gray-to-Binary Converter
- Day 10: 4-bit Adder-Subtractor Circuit
- Day 11: A Simple ALU
- Day 12: Sequence Detection
- Day 13: Priority Arbiter
- Day 14: Round-robin Arbiter
- Day 15: APB Master
- Day 16: A Simple Memory Module
- Day 17: Different Ways of Implementing a Multiplexer
- Day 18: Binary to One-Hot Converter
- Day 19: Register File
- Day 20: 4-bit Serial Adder
- Day 21: Class based Testbenches (A Refresher)
- Day 22: Class based Testbenches (A Refresher)
- Day 23: Class based Testbenches (A Refresher)
- Day 24: Interface
- Day 25: Interface
- Day 26: Interface
- Day 27: Pattern Generation using Constraints
- Day 28: FIFO Verification using Queues
- Day 29: Associative Arrays
- Day 30: Events
- Day 31: Mailboxes
- Day 32: Functions vs Tasks