kobalicek / amdtweak Goto Github PK
View Code? Open in Web Editor NEWA library that can be used to manipulate ATOM and PowerPlay (PP) tables of AMDGPUs
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awoelfel anjinmeili wiz avert chazu lucie2a pilsy jam3st 0xb1000000 vaibhavgupta3110 candiceflower fgy58963 nwops gnusuari0 olealgoritme fractalyse wsy2220 butinor nanom1tamdtweak's Issues
RX580 warning, writing pp table back crashes driver
When I run sudo ./amdtweak --card 0 --read-card-pp --print the first line printed is WARNING: 'HardLimitTable': Couldn't find versioned type 'HardLimitTable$1'
When trying to make what I think of as a safe like this:
sudo ./amdtweak --card 0 --read-card-pp --set FanTable.TargetTemperature=70 --write-card-pp
The amdgpu driver either just completely stops functioning or prints a kernel panic before locking up the machine.
As for what I'm trying to achieve: I'm trying to undervolt my card to see if I can improve the thermals a little bit.
WARNING: 'HardLimitTable': Couldn't find versioned type 'HardLimitTable$1'
Card '0': {
"StructureSize": 848,
"TableFormatRevision": 7,
"TableContentRevision": 1,
"RevisionId": 0,
"TableSize": 77,
"GoldenPPId": 1699,
"GoldenRevision": 10388,
"FormatId": 25,
"VoltageTime": 0,
"PlatformCaps": 33587202,
"SocClockMaxOD": 0,
"MemClockMaxOD": 0,
"PowerControlLimit": 50,
"UlvVoltageOffset": 50,
"StateTable": {
"RevisionId": 1,
"NumEntries": 3,
"Entries": [
{
"SocClockIndexHigh": 0,
"SocClockIndexLow": 0,
"MemClockIndexHigh": 0,
"MemClockIndexLow": 0,
"PCIEGenLow": 0,
"PCIEGenHigh": 0,
"PCIELaneLow": 0,
"PCIELaneHigh": 0,
"Classification": 8,
"CapsAndSettings": 0,
"Classification2": 0,
"Reserved1": 0
},
{
"SocClockIndexHigh": 3,
"SocClockIndexLow": 0,
"MemClockIndexHigh": 1,
"MemClockIndexLow": 0,
"PCIEGenLow": 0,
"PCIEGenHigh": 0,
"PCIELaneLow": 0,
"PCIELaneHigh": 0,
"Classification": 5,
"CapsAndSettings": 16384,
"Classification2": 0,
"Reserved1": 0
},
{
"SocClockIndexHigh": 1,
"SocClockIndexLow": 0,
"MemClockIndexHigh": 0,
"MemClockIndexLow": 0,
"PCIEGenLow": 0,
"PCIEGenHigh": 0,
"PCIELaneLow": 0,
"PCIELaneHigh": 0,
"Classification": 1,
"CapsAndSettings": 0,
"Classification2": 1,
"Reserved1": 0
}
]
},
"FanTable": {
"RevisionId": 9,
"THyst": 3,
"TMin": 4000,
"TMed": 6500,
"THigh": 8500,
"PWMMin": 2000,
"PWMMed": 4000,
"PWMHigh": 6000,
"TMax": 10900,
"FanControlMode": 1,
"FanPWMMax": 100,
"FanOutputSensitivity": 4836,
"FanRPMMax": 2200,
"MinFanSocClockAcousticLimit": 91000,
"TargetTemperature": 80,
"MinimumPWMLimit": 20,
"Reserved1": 100
},
"ThermalController": {
"RevisionId": 1,
"ControlType": 23,
"I2CLine": 0,
"I2CAddress": 0,
"FanParameters": 128,
"FanMinRPM": 0,
"FanMaxRPM": 0,
"Reserved1": 0,
"Flags": 0
},
"Reserved1": 0,
"MemClockDependencyTable": {
"RevisionId": 0,
"NumEntries": 2,
"Entries": [
{
"Vddc": 0,
"Vddci": 850,
"VddcGfxOffset": 0,
"Mvdd": 1000,
"MemClock": 30000,
"Reserved1": 0
},
{
"Vddc": 11,
"Vddci": 950,
"VddcGfxOffset": 0,
"Mvdd": 1000,
"MemClock": 200000,
"Reserved1": 0
}
]
},
"SocClockDependencyTable": {
"RevisionId": 1,
"NumEntries": 8,
"Entries": [
{
"Vddc": 0,
"VddcOffset": 0,
"SocClock": 30000,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 128,
"SocClockOffset": 0
},
{
"Vddc": 1,
"VddcOffset": -26,
"SocClock": 60800,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
},
{
"Vddc": 2,
"VddcOffset": -26,
"SocClock": 91000,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 5000
},
{
"Vddc": 3,
"VddcOffset": -26,
"SocClock": 107700,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
},
{
"Vddc": 4,
"VddcOffset": -26,
"SocClock": 107700,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
},
{
"Vddc": 5,
"VddcOffset": -26,
"SocClock": 107700,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
},
{
"Vddc": 6,
"VddcOffset": -26,
"SocClock": 107700,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
},
{
"Vddc": 7,
"VddcOffset": 0,
"SocClock": 107700,
"EDCCurrent": 0,
"ReliabilityTemperature": 0,
"CKSOffsetAndDisable": 0,
"SocClockOffset": 0
}
]
},
"VddcLookupTable": {
"RevisionId": 0,
"NumEntries": 15,
"Entries": [
{
"Vdd": 800,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65282,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65283,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65284,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65285,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65286,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65287,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65288,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 850,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 900,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 950,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 1000,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 1050,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 1100,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 1150,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
}
]
},
"VddGfxLookupTable": {
"RevisionId": 0,
"NumEntries": 8,
"Entries": [
{
"Vdd": 900,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65282,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65283,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65284,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65285,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65286,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65287,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
},
{
"Vdd": 65288,
"CACLow": 0,
"CACMid": 0,
"CACHigh": 0
}
]
},
"MMDependencyTable": {
"RevisionId": 0,
"NumEntries": 8,
"Entries": [
{
"Vddc": 0,
"VddcGfxOffset": 0,
"DCLK": 58000,
"VCLK": 75000,
"ECLK": 63000,
"ACLK": 0,
"SAMUCLK": 57000
},
{
"Vddc": 8,
"VddcGfxOffset": -76,
"DCLK": 63000,
"VCLK": 80000,
"ECLK": 69000,
"ACLK": 0,
"SAMUCLK": 64000
},
{
"Vddc": 9,
"VddcGfxOffset": -101,
"DCLK": 68000,
"VCLK": 85000,
"ECLK": 75000,
"ACLK": 0,
"SAMUCLK": 70000
},
{
"Vddc": 10,
"VddcGfxOffset": -126,
"DCLK": 73000,
"VCLK": 89000,
"ECLK": 81000,
"ACLK": 0,
"SAMUCLK": 76000
},
{
"Vddc": 11,
"VddcGfxOffset": -151,
"DCLK": 77000,
"VCLK": 92000,
"ECLK": 86000,
"ACLK": 0,
"SAMUCLK": 81000
},
{
"Vddc": 12,
"VddcGfxOffset": -201,
"DCLK": 80000,
"VCLK": 95000,
"ECLK": 91000,
"ACLK": 0,
"SAMUCLK": 85000
},
{
"Vddc": 13,
"VddcGfxOffset": -251,
"DCLK": 83000,
"VCLK": 98000,
"ECLK": 96000,
"ACLK": 0,
"SAMUCLK": 88000
},
{
"Vddc": 14,
"VddcGfxOffset": 0,
"DCLK": 86000,
"VCLK": 100000,
"ECLK": 100000,
"ACLK": 0,
"SAMUCLK": 91000
}
]
},
"VCEStateTable": {
"RevisionId": 1,
"NumEntries": 6,
"Entries": [
{
"VCEClockIndex": 0,
"Flag": 0,
"SocClockIndex": 1,
"MemClockIndex": 1
},
{
"VCEClockIndex": 0,
"Flag": 1,
"SocClockIndex": 1,
"MemClockIndex": 1
},
{
"VCEClockIndex": 0,
"Flag": 2,
"SocClockIndex": 1,
"MemClockIndex": 1
},
{
"VCEClockIndex": 0,
"Flag": 2,
"SocClockIndex": 1,
"MemClockIndex": 1
},
{
"VCEClockIndex": 0,
"Flag": 2,
"SocClockIndex": 1,
"MemClockIndex": 1
},
{
"VCEClockIndex": 0,
"Flag": 2,
"SocClockIndex": 1,
"MemClockIndex": 1
}
]
},
"PPMTable": null,
"PowerTuneTable": {
"RevisionId": 4,
"TDP": 68,
"ConfigurableTDP": 0,
"TDC": 74,
"BatteryPowerLimit": 65,
"SmallPowerLimit": 65,
"LowCACLeakage": 0,
"HighCACLeakage": 0,
"MaximumPowerDeliveryLimit": 68,
"TjMax": 92,
"PowerTuneDataSetId": 0,
"EDCLimit": 0,
"SoftwareShutdownTemp": 94,
"ClockStretchAmount": 2,
"TemperatureLimitHotspot": 105,
"TemperatureLimitLiquid1": 80,
"TemperatureLimitLiquid2": 80,
"TemperatureLimitVrVddc": 115,
"TemperatureLimitVrMvdd": 115,
"TemperatureLimitPlx": 95,
"Liquid1I2CAddress": 0,
"Liquid2I2CAddress": 0,
"LiquidI2CLine": 144,
"VrI2CAddress": 16,
"VrI2CLine": 150,
"PlxI2CAddress": 0,
"PlxI2CLine": 144,
"Reserved1": 0
},
"HardLimitTable": {
"RevisionId": 1,
"NumEntries": 1
},
"PCIETable": {
"RevisionId": 1,
"NumEntries": 3,
"Entries": [
{
"PCIEGenSpeed": 2,
"PCIELaneWidth": 16,
"Reserved1": 0,
"PCIEClock": 0
},
{
"PCIEGenSpeed": 2,
"PCIELaneWidth": 16,
"Reserved1": 0,
"PCIEClock": 0
},
{
"PCIEGenSpeed": 2,
"PCIELaneWidth": 16,
"Reserved1": 0,
"PCIEClock": 0
}
]
},
"GPIOTable": {
"RevisionId": 0,
"VRHotTriggeredSocClockDPMIndex": 1,
"Reserved1": 0,
"Reserved2": 0,
"Reserved3": 0,
"Reserved4": 0,
"Reserved5": 0
},
"Reserved2": 62564,
"Reserved3": 1,
"Reserved4": 1875,
"Reserved5": 0,
"Reserved6": 0,
"Reserved7": 0
}Support PP Table of Version < 7
Could this be used to replicate the Navi reset bug kernel patch?
There is a kernel patch available here: https://forum.level1techs.com/t/navi-reset-kernel-patch/147547
This patch uses the PowerPlay tables to turn the graphics card off and on again. This is done to work around an issue that affects people passing a Navi graphics card into a VM, where the card does not properly get reset between VM starts, and the host needs to be completely restarted to allow the VM to boot up again.
The kernel patch is likely not being merged into the kernel for a long time, and the distro that I am using it makes it quite difficult to run a custom kernel. So I was wondering if this project could be used to achieve the same effect?
Thanks.
Can't write to file
write_file_pp command seems broken. Says to accept 1 argument, but checks for 0. And it seems to try to write the table back to live driver, instead of user's file. Saving to file is important for backup-restore purposes and also to verify the program operation before committing a change to live card.
Error : function writeFile(fileName, value, encoding) cannot work with binary data
Hi,
found some solution for bugs #4 #5 and #7 :
you want to use fs.writeFileSync() to write some binary data but the parms you are using are for UTF8 strings ... so this cannot work.
file: ./lib/iofs.js
lines: 146-154
Bug :
function writeFile(fileName, value, encoding) {
try {
fs.writeFileSync(fileName, String(value), encoding); <<<---
return true;
}
catch (ex) {
return false;
}
}
Fix :
// you can remove 'encoding' param, it won't be used anymore
function writeFile(fileName, value, encoding) {
try {
fs.writeFile(fileName, value); <<<---
return true;
}
catch (ex) {
return false;
}
}
AMD RX VEGA not supported
Hi,
after some more tests,
it is clear that AMD RX-Vega56/64 specs are not detected as it should:
WARNING: 'GfxClockDependencyTable': Couldn't find versioned type 'GfxClockDependencyTable$1'
WARNING: 'VddcLookupTable': Couldn't find versioned type 'VoltageLookupTable$1'
WARNING: 'VddMemLookupTable': Couldn't find versioned type 'VoltageLookupTable$1'
WARNING: 'MMDependencyTable': Couldn't find versioned type 'MMDependencyTable$1'
WARNING: 'VddciLookupTable': Couldn't find versioned type 'VoltageLookupTable$1'
WARNING: 'PCIETable': Couldn't find versioned type 'PCIETable$2'
.../... blablabla .../...
Can you point me:
- where to find the spec of Vega PP_tables (let says, giving a sample for a RX480)
- where to put those specs in amdtweak (let says, giving a sample for a RX480)
so I can update the code for Vega56/64.
I will upload a pp_table and a bios extracted from my RX_Vega56 / Bios-Moded Vega64.
Best regards,
Missing some info about "--read_file_pp" usage
After some check in code,
you should document usage of method __read_file_pp.
when doing something like this :
./amdtweak --verbose --read-file-pp ../pp_tables/card_0.raw_pp_table --print
it doesn't do anything because __read_file_pp() doesn't allocate memory, nor buildup any card index list / structure to load data into it from the user provided file.
./amdtweak --verbose --card 0 --read-file-pp ../pp_tables/card_0.raw_pp_table --print
do work as method __card() has been called and so there is some memory where to put the data from the user provided file.
Possible fix:
- document the expected behavior
- issue an error when __read_file_pp() is called without any allocated memory
- add a check in __read_file_pp() before to load user provided file and allocate required data structure, memory etc..., with a call to __card() or something similar.
best regards,
print bios and other information
I am interested in the non power_play table information like bios info and vram module info.
I can't seem to print this information out though.
Below is the code that I used to test this with:
const binlib = require("./lib/binlib.js");
const iofs = require("./lib/iofs.js");
const vbios = require("./lib/vbios.js");
const CARD_ID = 0;
const DUMP = true;
const OVERWRITE = false;
const CARD_PP = `/sys/class/drm/card${CARD_ID}/device/pp_table`;
const buf = fs.readFileSync(CARD_PP);
console.log(JSON.stringify(vbios.$readObject({ buffer: buf, type: vbios.VRAMModule }), null, 2));
{}
AMD Radeon VII not supported
Hi, is it possible to have VEGA20 support ?
best regards.
Cannot write to pp table
I'm running linux 4.12 ( with the proprietary opencl kernel from amdgpu-pro, but it doesn't matter right? ) with an RX 470 and trying to reproduce the example in the Readme, I noticed I can't write to PowerTuneTable.TDP nor to PowerTuneTable.ConfigurableTDP. As soon as I do, the pp table becomes permanently ( until reboot ) irresponsive. As in cat /sys/class/drm/card0/device/pp_table never returns, amdtweak hangs forever if used to read it and radeon-profile hangs as well. Also, Unigine Valley slows down from 40 fps to 10. Is it because the clocks lower to the mininum? I don't know, I have no way to check without the pp table lol. Any clue? I haven't tried writing any other variable yet, but I suspect it will be the same
create uuid to gpu ?
Each of my gpus is a snowflake and I need to a UUID in order to identify each of them. However, I can't seem to find any kind of unique identifier in the bios or card (except on a sticker externally). If I created a UUID for each card and stored that in the GPU. How would I go about committing data to the GPU.
Additionally I don't want a bios mod overwriting a UUID.
strap timings
do you know if is possible (or how) to change memory strapping times ?
Error in amdtweak.js
Topic : write_file_pp try to write to device pp_table and not to user provided file name.
error :
321 __write_file_pp(args) {
322 if (args.length !== 0)
323 this.error('--write-file-pp' command accepts exactly one argument);
.../...
330 const fileName = ${Utils.pathOfCard(id)}/device/pp_table;
.../...
345 this.warning(Couldn't write PP table of card '${id}'**, are you root?**);
fix :
321 __write_file_pp(args) {
322 if (args.length !== 1)
323 this.error('--write-file-pp' command accepts exactly one argument);
.../...
330 const fileName = this.checkFileName(args[0]);
.../...
345 this.warning(Couldn't write PP table of card '${id}' **to file '${fileName}', do you have write access?**);
run amdtweak errors！
05:23 AM ethos@2e1b01 192.168.10.104 [miner disallowed] /home/amdtweak # sudo ./amdtweak
/home/amdtweak/amdtweak.js:3
const fs = require("fs");
^^^^^
SyntaxError: Use of const in strict mode.
at Module._compile (module.js:439:25)
at Object.Module._extensions..js (module.js:474:10)
at Module.load (module.js:356:32)
at Function.Module._load (module.js:312:12)
at Function.Module.runMain (module.js:497:10)
at startup (node.js:119:16)
at node.js:902:3
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