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When the host supports RISC-V AIA, the KVM kernel module will provide in-kernel AIA virtualization and the QEMU should:

1. Detect and configure in-kernel AIA support
2. Generate AIA DT nodes instead of PLIC DT node

Need in-kernel AIA virtualization in KVM RISC-V (#39)

Not started yet.

Allow KVM user-space to access Guest VCPU virtual HS-mode state using KVM ONE_REG interface.

When the host supports RISC-V AIA, the KVM kernel module will provide in-kernel AIA virtualization and the KVMTOOL should:

1. Detect and configure in-kernel AIA support
2. Generate AIA DT nodes instead of PLIC DT node

Need in-kernel AIA virtualization in KVM RISC-V (#39)

When KVM RISC-V supports nested virtualization, the QEMU RISC-V should:

1. Append "h" to to the HART ISA string in generated DTB
2. Save/restore virtual HS-mode state for QEMU Guest/VM migration

Need KVM RISC-V nested virtualization support (#3)
Need KVM ONE_REG interface for accessing Guest VCPU virtual HS-mode state (#15)

Not started yet.

The QEMU RISC-V should support save/restore of Guest/VM when using KVM RISC-V accleration.

Work in progress.

When the host supports RISC-V V-Extension, the QEMU RISC-V should:

1. Append "v" to the HART ISA string in generated DTB
2. Save/restore V-extension state for Guest/VM migration

Need RISC-V V-extension virtualization in KVM RISC-V (#13)
Need KVM ONE_REG interface for accessing Guest VCPU V-extension state (#14)

Not started yet.

The AIA APLIC is a new interrupt controller so implement Linux driver for it.

Add trace points at interesting places in KVM RISC-V for gathering interesting stats.

Not started yet.

We need a standard hypervisor (and platform) independent way to PowerOff or Reboot a Guest/VM.

A proposal for SBI System Reset (SRST) extension in already under discussion.
(Refer, riscv-non-isa/riscv-sbi-doc#39)

Implement a new Linux SBI PMU driver for Linux RISC-V. The driver will mostly access RISC-V PMU counters directly but it will use SBI PMU calls to discover and configure RISC-V PMU counters.

Need SBI specification changes first. (#10)

Not started yet.

We will first get Xvisor RISC-V running inside KVM RISC-V (and vice-versa). The Xvisor RISC-V has nested MMU test suite which can be helpful in implementing Stage2 MMU emulation for KVM RISC-V.

Finally, we will get KVM RISC-V running inside KVM RISC-V.

Work in progress.

We have to extend the existing QEMU KVM driver in Libvirt to support QEMU KVM RISC-V.

Need QEMU KVM RISC-V support for this (#25).
Need QEMU KVM RISC-V Guest/VM migration support for this (#26).

Extend SBI specification to include SBI performance monitoring unit (PMU) extension

The SBI PMU draft proposal is under review on RISC-V Unix Platform mailing list.

Work in progress.

Allow KVM user-space to access Guest VCPU V-extension state using KVM ONE_REG interface.

Hi,
I really want to know the meaning of IMSIC HW guest file? Is that different from guest file? Or is that related to devices?
hope receive your reply as soon,
thanks

Patches available on KVM-RISCV mailing list: https://lkml.org/lkml/2020/8/3/1055

Need more reviews for these patches.

Extend KVM unit tests to support testing KVM RISC-V.

Not started yet.

Implement SBI PMU extension in KVM RISC-V so that Guest/VM has a way to access RISC-V PMU counters.

Need SBI PMU defined in SBI specification (#10)
Need Linux SBI PMU driver (#11)

Yet to be started.

Implement lazy save/restore of V-extension registers in KVM RISC-V

Yet to be started.

Extend SBI specification to include SBI para-virt time scaling (PTS) extension. The SBI PTS calls will be VDSO-style calls using which Guest/VM can know the scaling to be done on TIME CSR value before using it.

Not started yet.

Extend KVM self tests to support testing KVM RISC-V.

Not started yet.

Implement SBI SRST extension in KVM RISC-V so that we can PowerOff or Reboot a Guest/VM.

Need SBI SRST defined in SBI specification (#19)
Need SBI SRST to be used by Linux RISC-V SBI (#20)

Yet to be started.

We need to extend QEMU RISC-V to support KVM RISC-V as acceleration.

Patches are already available on QEMU RISC-V mailing list.

Need more reviews for these patches.

Sorry for help, according to the output 'Placing fdt at 0x81800000 - 0x87ffffff' and the code of kvmtool, I should load fdt file to gpa:0x81800000.
But I cannot find the fdt file. I only find that the kvmtool load the kernel file (build-riscv64/arch/riscv/boot/Image) to gpa:0x80200000. So where can I find the fdt file?
Thank you so much!

When KVM RISC-V supports nested virtualization, the KVMTOOL should:

1. Append "h" to to the HART ISA string in generated DTB
2. Dump virtual HS-mode state in kvm_cpu__show_registers()

Need KVM RISC-V nested virtualization support (#3)
Need KVM ONE_REG interface for accessing Guest VCPU virtual HS-mode state (#15)

The AIA IMSIC is a new interrupt controller so implement Linux driver for it.

Implement SBI PTS extension in KVM RISC-V so that we can allow migrating Guest/VM across Hosts with different timer frequency.

Need SBI PTS defined in SBI specification (#7)
Need SBI PTS to be used by Linux RISC-V timer driver (#8)

Yet to be started.

The Linux RISC-V kernel should detect and use SBI SRST extension whenever available.

Need SBI specification changes first. (#19)

RFC Patches already available on Linux RISC-V mailing list (https://lkml.org/lkml/2020/9/26/40)

Need more reviews for these patches.

I have reviewed all your KVM patches about riscv, I admire your ability very much，But can't find the HiFive Unleashed board to verify and study it.

The need to extend the Linux RISC-V timer driver for using SBI PTS extension when available

Need SBI specification changes first. (#7)

Yet to be started.

Implement SBI PSTA extension in KVM RISC-V so that Linux running as KVM Guest/VM can use steal time accounting information provided by the KVM RISC-V hypervisor.

Need to SBI PSTA defined in SBI specification (#4)
Need SBI PSTA based para-virt ops for Linux RISC-V (#5)

Yet to be started.

Implement SBI PSTA based para-virt ops for Linux RISC-V so that Linux kernel scheduler can account to stolen time when running inside Guest/VM

Need to SBI specification changes first. (#4)

Yet to be started.

I only found a modification of vsatp here. If csr->vsatp is different with CSR_VSATP, I think hfence.vma should be added after write CSR_VSATP.

BTW, I can't find the modification of csr->vsatp. Could you help to point out how csr->vsatp was modified?

Thanks

The AIA CSRs and AIA IMSIC has interrupt virtualization support so the KVM RISC-V kernel module can leverage this for hardware assisted AIA emulation/virtualization.

Need AIA support in Linux RISC-V INTC driver (#36)
Need Linux IMSIC driver (#37)
Need Linux APLIC driver (#38)

To use AIA extended local interrupts, the Linux RISC-V INTC driver must detect and use AIA CSRs.

Sorry for help. I want to learn about the IPI.
I found that hideleg got 1U << IRQ_VS_SOFT, and that means all the IRQ_VS_SOFT interrupts will be delegate to VS mode.
Then I found "smp_send_reschedule(cpu)" in kvm_vcpu_kick. And it send IPI to the guest. Is the IPI a IRQ_VS_SOFT? If so, the IPI will be handle by the VS mode, and it won't be kicked to hypervisor in HS mode. So I must misunderstand something. Can U help me?

When the host supports RISC-V V-Extension, the KVMTOOL should:

1. Append "v" to the HART ISA string in generated DTB
2. Dump V-extension state in kvm_cpu__show_registers()

Need RISC-V V-extension virtualization in KVM RISC-V (#13)
Need KVM ONE_REG interface for accessing Guest VCPU V-extension state (#14)

Not started yet.

We need to extend KVMTOOL to support KVM RISC-V.

Patches are already available on KVM RISC-V mailing list (https://www.spinics.net/lists/kvm/msg220397.html)

Need more reviews for these patches.

Sorry, but I read the value of MISA and it is 0x800000000014112d.
the 8th bit (bit[7]) is 0, so this means this version does not support H extension for hypervisor?
Thank you for help!

Form riscv-privilegaed document section 5.2.7, htval is allowed to be written to zero, so kvm software may not be able to use this register.
When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits.

Extend SBI specification to include SBI para-virt steal time accounting (PSTA) extension

Not started yet.