Comments (6)
from board.
related to #19
from board.
Addressed by Daniel Golle's work on the SPI chip.
May require a different chip type.
Moved to Phase 2 testing to check design solution.
from board.
We have agreed to change the specification of the 2nd prototype to 16MB.
from board.
While using the 32MB flash chip w25q256fv, if we connect the current pin1(HOLD) and pin3(/RESET) together, since pin1 is connected to SYS_RST_L . while the QCA9558 reboot, it will send a low to SYS_RST_L so to reset the flash. This can fix this reset issue.
from board.
This is fixed in phase2 (MegaBoard v1.1 / Core v0.2)
from board.
Related Issues (20)
- Move PCIe1 device HOT 1
- Change PCIe1 3.3V source HOT 2
- Change GPS 3.3V source HOT 1
- Individual disable for PCIe0 and 1 HOT 1
- Add hack ethernet port HOT 1
- Add magnetics board option HOT 1
- Power domain isolation HOT 2
- Shorten GPS uart path HOT 1
- Add JTAG connector HOT 1
- General track and vias review
- Complete BOM HOT 7
- Improve impedance of PCIe routing HOT 4
- Remove SPI connection from watchdog to core board (introduced by mistake in the Eagle to Kicad migration) HOT 1
- Improve Ethernet differential pair impedance and reduce series resistance HOT 2
- Missing holes in PCB HOT 6
- Missing Core Board? HOT 2
- Properly design coupled transmission lines HOT 2
- Add a way to disconnect the power to the board through GPIO HOT 3
- General Silk screen check
- Change JATG pull down resistors Value
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from board.