librerouterorg / board

LibreRouter hardware repository

Development moved to https://gitlab.com/librerouter/boards

board's Issues

ANT 2 Circuit Error

L/C high pass filter circuit is incorrect for ANT 2

Circuit is correct for ANT3 (L25/C165) or ANT1 (L31/C278)

See Issue 13 also.

PCB's process parameter

Hi,
What is the PCB's process parameter?

Add JTAG connector

The JTAG is accessible on expose IOs connector. Will be more easy if it is a separated connector.

Connector 2x5 din will be added with JTAGice MkII layout:

Hardware Reset Operation: Watchdog

GPIO 2 connected to ATTINY hardware reset chip (schematic pp 6)

GPIO2, 3 Designated as EJTAG_TDO, EJTAG_TMS

GPIO2, 3 connected to WAKE_L_0, WAKE_L_1 line on PCIe connectors. (schematic pp15)

Is there a conflict on GPIO 2??

Individual disable for PCIe0 and 1

The disable pin of both PCIe devices is connected to the same GPIO of the core board.

The GPIO12 will be kept connected to PCIe0 disable only.
The GPIO14 will be connected to PCIe1 disable.

ANT3 connector - no signal

The ANT3 connector on the primary QCA9558 radio is not producing any signal on TG sample board.
ANT1 produces 16dBm signal, and ANT2 produces 6dBm signal on TG sample board.

Note that to get max power output, the wifi Country parameter has to be set to non-default value eg AU
TxPower max on QCA9558 displays in "iw dev" output as "31dBm" with Country set to AU.

Change PCIe1 3.3V source

The PCIe1 is connected to general 3.3V power supply and it's supposed to be +3V3_PCIE.

The connection will be changed on the sch and rerouted on PCB.

Remove SPI connection from watchdog to core board (introduced by mistake in the Eagle to Kicad migration)

This connection was introduced by mistake while migrating from eagle.

Missing Core Board?

Am I looking in the wrong place or is the kicad project for the core board missing? I only see mega_board in the designs folder.

Add magnetics board option

In the future we want to use the magnetics in a separated board for quick exchange.

Further discussion needs to be made on this matter.

Shorten GPS uart path

The GPS uart path is too long.

The GPS connector will be moved close to de core board.

PoE is not working

PoE is not working.
Probably due to errors in Ethernet connector wiring

TODO - check operation of PoE passthrough switch circuit.

Better PoE power handling in both LAN and WAN ports

We should add a low voltage diode from the PoE to the PoE pass port as some current is going from the PoE_pass that at least powers a LED, being very confusing.

Board hangs after reboot.

Reboot without power-cycling doesn't work.

Dragino PoE injector does not support 1000mbps

As this injector doesn't have magnetics the power source pair only conducts the power and not the signal

GPS module does not lock (signal issues)

The GPS module never locks to the GPS satellite signal when connected to the Mega Board.
If the GPS module works ok if it is powered by an external source.

Main culprit could be power source noise from the RT7272 DC-DC switching modules. This modules oscillate at 500MHz that is nearly 1/3 of the GPS signal frequency. So signal jamming from the power source could be the problem in a mix of conducted or emited noise.

The GPS module has a ferrite ( PZ2012D800-3R0TF) in series for filtering.

we don't have a bootloader

We currently use a U-Boot binary which comes from some other QCA board.
We could port Barebox for the QCA9558 or forget about our ideals and use BREED...

USB LED Operation

This LED does not light at any time, including initial power up when all other LEDS are lit for a short time.

The USB LED is driven from GPIO20 and is lit when GPIO20 line is pulled low by the GPIO test script.

Missing holes in PCB

When we change the design from eagle to kicad some holes disappear.

Pin connection difference between PCIe0 and PCIe1

The 37th pin on PCIe1 is connected to ground but not on PCIe0.

Accordingly to PCIe M2 mSATA pinout, the pin must be connected to GND. But is reserved on PCIe minicard pinout. So, one of the two is wrong.

Proposal: Add 0Ohm resistor to ground in both cases and test.

PoE and PoE Passthrough overheats magnetics

T1 magnetics (QT48A03) gets very very hot in one minute (after activation) when doing PoE passthrough to another LR (total power measured at the power source: 14W )

Some notes:

• QT48A03 datasheet doesn't say it is PoE compliant.
• Here are some magnetics that supports PoE http://www.silvertel.com/poe-documents/88-poe-magnetics.html
• PoE (and PoE passthrough) is using only one pair. TODO: Perform the same test with the other pairs in parallel.

PCIe mounting holes are misaligned

PCIe mounting holes are misaligned.

Dragino is aware of this issue and it is being addressed in the updated version of the PCIe board.

Firmware Build / Loading

We are unable to build and load new firmware on the prototype boards.
The current firmware is a binary copy of firmware from a reference board.
Sysupgrade does not appear to work in the current firmware.
Loading new firmware requires binary copying of kernel and rootfs partitions via UBoot.
It is not obvious how to generate these binaries from the normal LEDE build process for the AP135 target.

Input voltage is <= 30V

There is a problem when voltage go over 30V (with and without PoE). Consumption goes from 4.7W@30V to 7W@32V. The component that gets very hot seems to be V1 BC301N-D Gas Discharge Tube.
So the usable range is 8V to 29V at least in the board I measured.

SWRST Operation

The SWRST line is driven by GPIO 17, but this GPIO fails when exercised with the test script.
Attempting to drive this GPIO from the test program fails as it is not exported to create the directory in /sys/class/gpio
It does not appear to have any special function.
It may be reserved by current firmware.

Improve impedance of PCIe routing

Differential impedance must be 100ohm.

Current Mega board calculated impedance is 130ohm.

One proposed solution:

Internal RF cables may disconnect or shortcircuit

Provide a good way to tie the cables to the megaboard so that we can use better cables.
Take in consideration that cables of different radios must not touch to minimize crosstalk.

Providing good support for the cables we can use better/heavier cables without disconnecting issues.

Prototypes have fake and reused MAC addresses

Compare these two outputs, produced in two different nodes running LibreRouters v1.0 with two HPM5G modules each

root@czuk-bbone:~# ethtool -P eth0
Permanent address: 14:3d:f2:cc:92:72
root@czuk-bbone:~# ethtool -P eth1
Permanent address: 14:3d:f2:cc:92:71
root@czuk-bbone:~# ethtool -P wlan0-adhoc
Permanent address: 00:11:7f:13:36:36
root@czuk-bbone:~# ethtool -P wlan1-adhoc
Permanent address: 00:02:03:04:05:06
root@czuk-bbone:~# ethtool -P wlan2-adhoc
Permanent address: 00:02:03:04:05:06

root@oncelotes-bbone:~# ethtool -P eth0
Permanent address: 14:3d:f2:cc:92:72
root@oncelotes-bbone:~# ethtool -P eth1
Permanent address: 14:3d:f2:cc:92:71
root@oncelotes-bbone:~# ethtool -P wlan0-ap
Permanent address: 00:11:7f:13:36:36
root@oncelotes-bbone:~# ethtool -P wlan1-adhoc
Permanent address: 00:02:03:04:05:06
root@oncelotes-bbone:~# ethtool -P wlan2-adhoc
Permanent address: 00:02:03:04:05:06

This makes it impossible to mesh out-of-the-box either via wireless or ethernet, since MAC address on eth0 of czuk-bbone is identical to the MAC of eth0 in oncelotes-bbone (and all the other eth0 in other LibreRouters). Same happens for wlan0.

With HPM5G modules the problem gets worse, since it's very unexpected to have a system with two different physical interfaces with identical MAC address. 80211s kernel code warns repeatedly since boot (this was reported upstream https://www.spinics.net/lists/linux-wireless/msg168634.html)

Current workaround we do is to generate random macaddresses on first boot, and hardcode them in uci config, so those are used instead.

Change GPS 3.3V source

The PCIe1 is connected to +3V3_PCIE power supply and it's supposed to be general 3.3V.

The connection will be changed on the sch and rerouted on PCB.

Board Mounting

There are limited mounting holes which correspond to the mounting points in the proposed enclosure.
But it is needs to be looked at to ensure that the board will be mechanically secure.

Also, possibly worthwhile to provide additional holes in each corner and middle of the board so that it can be easily mounted in simple box enclosures.

Improve Ethernet differential pair impedance and reduce series resistance

The differential routing of the ethernet lines is not compliant with the impedance nether with the carrying power.

PoE passthrough circuit R32 is too low

R32=10k acts as voltage divisor with R57=100k.
Si4435DDY transistor has max Vgs = +-20V and VTh = -3V. The other transistor, BSS137, has abs max voltages of 50V so no problem.

Requirements from datasheet: at 8V DC input VGS < -3V and at 36V VGS > -20.

Solution:
Change resistor value of R32 to 68K.

The divisor R57=100k and R32=68K must work as it is a 0.4 divisor. IN at 8V -> -3.2Vgs and IN 36V -> -14.4V

Move PCIe1 device

Aimed to fix the cross talk problem between PCIe0 and PCIe1.

The PCIe1 connector must be move far as possible from PCIe0 and to the other side of the board.

The LEDs block will be moved to make place for the PCIe1.
The upper right anchor hole is not being used, it will be deleted.
The cutout area will be filled with gnd plane.

Add internal header for Core9558 ethernet ports not used

The Core9558 board have four ethernet ports expose in the external pins P1, P2, P3, P4.

P3 and P4 are being used for external RJ45 connectors.
P1 and P2 are not being used.

Proposal: add internal connectors for future use.

Status LED Operation

This LED operates only at initial power up for a brief period.
The LED is driven from GPIO23.
Attempting to drive this GPIO from the test program fails as it is not exported to create the directory in /sys/class/gpio
The QCA9558 Datasheet does not show any special function for this GPIO so it is not obvious why it fails the test program.

Properly design coupled transmission lines

We are using coupled microstrips for the MegaBoard differential pairs (PCIe, USB, etc) and we are not taking in consideration the distance between the line and the groud plane at the sides.

Related to #54

Improve 5.8GHz antenna's pigtails

5.8GHz phase 2 antennas have the pigtail soldered directly to the antenna and the cable is not tightened or fastened in any way, so accidental pulling from the pigtail may break the antenna or the soldering.

Screen print font

Screen print font is too small to read.
This is important for identifying the I/O connectors particularly.

General track and vias review

There are some vias and tracks not in the best shape.

Vias will be ordered.
Extra tacks will be deleted.
Power tracks will be changed to zones.

Further discussion is needed before this change are made.

2.4 Ghz radio issue

Hi,
I open this issue to document the bug of the Qualcomm chipset so we can reach out to find a solution.
Please @dragino could you tell us a more?

Rx Sensitivity

Rx Sensitivity of the QCA 9558 SoC seems to be low, and varies between ANT connectors on some sample boards.

Testing on TG sample board indicates that Rx Sensitivity is ~10dB lower than that of a comparison WR703 device, but is the same (within 2dB) for all ANT connectors.
Testing on Elektra sample boards indicates ~20dB below comparison level, and with ~6dB variability between ANT connectors.

This is not an RF calibration problem. It is likely to be a problem with components in the RF output circuits around the PA, LNA and T/R switch components.

Link LED Operation

The Link0 and Link 1 LEDs are only lit briefly at initial power up.

The LINK LEDs are shown on schematic pp 11 as being driven by the following signals:

LINK0 S17_LEDn_3 , S17_LEDn1000_3
LINK 1 S17_LEDn_4 , S17_LEDn1000_4

These signals are referenced on schematic pp 9 but don't appear to be connected to any other device.
They do not appear anywhere else in the schematic.

GPIO Operation

GPIOs 0, 1, 2, 3, 4, 13 fail testing as simple GPIOs.
These GPIOs have reserved functions and will require system configuration to test operation.

GPIOs 17, 23 fail testing as simple GPIOs.
These GPIOs do not appear to have reserved functions.

It is possible that they have been used by kernel code in the firmwware which was copied from a different board. This will be resolved when firmware is built for the board.

GPIO17 is used for SWRST line (from Reset Button SW1 and I/O connectors)
GPIO23 is used for STATUS LED

See QCA9558 Datasheet

• pp70 Table 3-16 Default GPIO Signals
• pp47 Bootstrap Options

Complete BOM

The BOM is not fully defined.

We will copy the components that are defined in the eagle design and define thous that are not.

Heatsinks

Heatsinks are not fitted to the QCA9558 and PA chips, or the PCIe radio modules.

The QCA9558 chip surface runs 25-30C above ambient temperature with no heatsink at idle.
The chips are likely to overheat and fail with high data throughput.

LEDs for 5GHz WLAN Operation

LEDs for 5GHz WLAN are both lit with one board installed.

The 5G WLAN LEDs are shown on schematic pp 11 as being driven by signals:
5G_WLAN_LED_0
5G_WLAN_LED_1
These signals appear on schematic pp 15 and 16 respectively as connected to the PCIe connectors Pin 44.
The circuit looks correct. There is no obvious reason why both LEDs should light when only one PCIe board is installed.
Elektra has confirmed the issue on her sample board also.

Add hack ethernet port

There is two ethernet ports that are not being used.

The port ETH0 of the core board will be connected to a 2x5 din connector close to the board.

The pinout will be:

1. TRX1-
2. TRX2+
3. TRX1+
4. TRX2-
5. TRX0-
6. TRX3+
7. TRX0+
8. TRX3-
9. GND
10. GND

The USB din header must be moved to the left and rotated 90deg. The 5V power net must be moved to achieve this.

The ethernet header will be route at bottom using vias close to the core board.

Ethernet connector wiring

Onboard Ethernet connectors are incorrectly wired

Power domain isolation

There are some power domain that can be isolated for enhance general power domain noice.

The next power domains will be separated with choke inductor:

• PCIe0 and PCIe1 3.3V
• PCIe0 and PCIe1 5V
• USB 5V_1
• Core 3.3V

Board hangs when power cycled with serial TTL connected

When attaching power to Prototype V1 board with a serial ttl attached (ground/rx/tx pins) boot seems to hang

U-Boot 1.1.4 (Apr 19 2014 - 00:17:22)

ap135 - Scorpion 1.0DRAM:
sri
Scorpion 1.0
ath_ddr_initial_config(233): (32bit) ddr1 init
tap = 0x00000002
Tap (low, high) = (0x4, 0x1e)
Tap values = (0x11, 0x11, 0x11, 0x11)
 4 MB
Top of RAM usable for U-Boot at: 80400000
Reserving 207k for U-Boot at: 803cc000
Reserving 192k for malloc() at: 8039c000
Reserving 44 Bytes for Board Info at: 8039bfd4
Reserving 36 Bytes for Global Data at: 8039bfb0
Reserving 128k for boot params() at: 8037bfb0
Stack Pointer at: 8037bf98

Not sure if it is related to #3

(refrenced tomeshnet/meshstream#7)