[Interrupts] Current interrupt C generation inadequate for CBM machines about llvm-mos

[jtgans]

I've created a PR, #458, that resolves this problem by adding a new function attribute called "wedge" that takes a single 16-bit integer value, and alters the return lowering to use a TailJMP to force register saving, properly, etc.

[mysterymath]

Ideally, I want my ISR to only save what is transitively calculated from other function calls that I make use of, and the compiler has that information.

At least right now, the compiler can't actually do that. Register allocation in LLVM isn't by default done in any particular order, so the set of registers used by a callee may not be available when the caller is being compiled. That means that the caller is forced to assume that the callee can touch any caller-saved register, and if it's an ISR, it has to save all of them on behalf of the interrupted routine.

That being said, there is an infrastructure in LLVM to do "interprocedural register allocation". This more or less amounts to performing codegen in as close to "callee-first" order as is possible, then propagating register usage information about call sites to callers. I wasn't easily able to get this working on llvm-mos though; the code was added for IBM System V (IIRC), and it looked either unfinished or atrophied last I tried it.

Even with interprocedural register allocation, a callee might misjudge the cost of using a caller-saved register, since it wouldn't know that it was called inside an interrupt and that such registers aren't free. The whole register allocator architecture basically assumes caller-saved registers are free; so implicitly implying an AXY calling convention to anything called within an interrupt seems prudent anyway.

This convention would make every imaginary register a callee-saved register. This doesn't mean they would actually ever need to be saved, since the zero page allocator will automatically "promote" callee-saved register uses to unique zero page locations when profitable. That would tend to produce the usual style for hand-written interrupt handlers: AXY used freely, and a portion of the zero page exclusively dedicated for use within the ISR.