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A demo system for Ibex including debug support and some peripherals

License: Apache License 2.0

Tcl 9.94% SystemVerilog 21.74% CMake 1.23% Assembly 0.69% C 41.69% Shell 0.36% Python 12.07% C++ 0.96% Dockerfile 1.02% Nix 1.28% Rust 9.04%

ibex-demo-system's Introduction

Ibex Demo System

Ibex demo system block diagram

This an example RISC-V SoC targeting the Arty-A7 FPGA board. It comprises the lowRISC Ibex core along with the following features:

  • RISC-V debug support (using the PULP RISC-V Debug Module)
  • UART
  • GPIO
  • PWM
  • Timer
  • SPI
  • A basic peripheral to write ASCII output to a file and halt simulation from software

Debug can be used via a USB connection to the Arty-A7 board. No external JTAG probe is required.

Arty A7 FPGA showing the Mandelbrot set

Software Requirements

Container Guide

There is a prebuilt container of tools available you may want to use to get started quickly. There are instructions for building the container for either Docker/Podman located in ./container/README.md.

Linux/MacOS

A container image may be provided to you in the form of a tarball. You can load the containerfile by running:

sudo docker load < ibex_demo_image.tar
# OR
podman load < ibex_demo_image.tar

If you already have a container file, you can start the container by running:

sudo docker run -it --rm \
  -p 6080:6080 \
  -p 3333:3333 \
  -v $(pwd):/home/dev/demo:Z \
  ibex

OR

podman unshare chown 1000:1000 -R .
podman run -it --rm \
  -p 6080:6080 \
  -p 3333:3333 \
  -v $(pwd):/home/dev/demo:Z \
  ibex
podman unshare chown 0:0 -R .

To access the container once running, go to http://localhost:6080/vnc.html.

If you want to program the FPGA from the container, let's find out which bus and device the Arty is on:

$ lsusb
...
Bus 00X Device 00Y: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
...

Where X and Y are numbers. Please note down what X and Y is for you (this will change if you unplug and replug your FPGA).

Then run Docker with the following parameters:

sudo docker run -it --rm \
  -p 6080:6080 \
  -p 3333:3333 \
  -v $(pwd):/home/dev/demo:Z \
  --privileged \
  --device=/dev/bus/usb/00X/00Y \
  --device=/dev/ttyUSB1 \
  ibex

Windows

Run a command prompt in administrator mode and type:

cd "C:\Program Files\Docker\Docker"
.\DockerCli.exe -SwitchLinuxEngine

In case you have a tarball of the docker image, run:

docker load -i ibex_demo_image.tar

Go to the folder where you have decompressed the demo system repository:

docker run -it --rm -p 6080:6080 -p 3333:3333 -v %cd%:/home/dev/demo:Z ibex

Add udev rules for our device

For both the container and the native setups you will need to add user device permissions for our FPGA board. The following instructions are for Linux-based systems and are needed for the programmer to access the development board.

Arty-A7

sudo su
cat <<EOF > /etc/udev/rules.d/90-arty-a7.rules
# Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
# used on Digilent boards
ACTION=="add|change", SUBSYSTEM=="usb|tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", ATTRS{manufacturer}=="Digilent", MODE="0666"

# Future Technology Devices International, Ltd FT232 Serial (UART) IC
ACTION=="add|change", SUBSYSTEM=="usb|tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="0666"
EOF

exit

openFPGAloader

sudo su
cat <<EOF > /etc/udev/rules.d/99-openfpgaloader.rules
# Copy this file to /etc/udev/rules.d/

ACTION!="add|change", GOTO="openfpgaloader_rules_end"

# gpiochip subsystem
SUBSYSTEM=="gpio", MODE="0664", GROUP="plugdev", TAG+="uaccess"

SUBSYSTEM!="usb|tty|hidraw", GOTO="openfpgaloader_rules_end"

# Original FT232/FT245 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"

# Original FT2232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev", TAG+="uaccess"

# Original FT4232 VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev", TAG+="uaccess"

# Original FT232H VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="664", GROUP="plugdev", TAG+="uaccess"

# Original FT231X VID:PID
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="664", GROUP="plugdev", TAG+="uaccess"

# anlogic cable
ATTRS{idVendor}=="0547", ATTRS{idProduct}=="1002", MODE="664", GROUP="plugdev", TAG+="uaccess"

# altera usb-blaster
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="664", GROUP="plugdev", TAG+="uaccess"
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="664", GROUP="plugdev", TAG+="uaccess"

# altera usb-blasterII - uninitialized
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="664", GROUP="plugdev", TAG+="uaccess"
# altera usb-blasterII - initialized
ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev", TAG+="uaccess"

# dirtyJTAG
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="c0ca", MODE="664", GROUP="plugdev", TAG+="uaccess"

# Jlink
ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="664", GROUP="plugdev", TAG+="uaccess"

# NXP LPC-Link2
ATTRS{idVendor}=="1fc9", ATTRS{idProduct}=="0090", MODE="664", GROUP="plugdev", TAG+="uaccess"

# NXP ARM mbed
ATTRS{idVendor}=="0d28", ATTRS{idProduct}=="0204", MODE="664", GROUP="plugdev", TAG+="uaccess"

# icebreaker bitsy
ATTRS{idVendor}=="1d50", ATTRS{idProduct}=="6146", MODE="664", GROUP="plugdev", TAG+="uaccess"

# orbtrace-mini dfu
ATTRS{idVendor}=="1209", ATTRS{idProduct}=="3442", MODE="664", GROUP="plugdev", TAG+="uaccess"

LABEL="openfpgaloader_rules_end"

EOF

exit

Run the following to reload the rules:

sudo udevadm control --reload-rules
sudo udevadm trigger

Add user to plugdev group:

sudo usermod -a $USER -G plugdev
Installing environment using Nix (*alternative*)

Nix Environment Setup

An alternative system for installing all of the project dependencies is provided using the Nix package manager. Once installed and the dependencies are fetched from the internet, you can enter a shell with all of the software required for building by running the command nix develop in the root directory of the project. To leave this environment, simply run exit.

Installing

Installing Nix

# Run the recommended nix multi-user installation
# https://nixos.org/download.html
# This is an interactive installer, just follow the prompts...
sh <(curl -L https://nixos.org/nix/install) --daemon

# Add some global configuration to nix to make use of the flakes and CLI experimental features.
mkdir -p $HOME/.config/nix
cat <<EOF > $HOME/.config/nix/nix.conf
experimental-features = nix-command flakes
warn-dirty = false
EOF

# Disable signatures when using nix copy to import from a store
# This allows us to easily import from a cache on a local USB
sudo su
mkdir -p /etc/nix
cat <<EOF >> /etc/nix/nix.conf
require-sigs = false
EOF
exit

# Reload the nix daemon to commit the config above
sudo systemctl restart nix-daemon.service

# You may now need to reload your shell, but check that nix is working by running this:
nix --version
> nix (Nix) 2.12.0

Installing Vivado using Nix

# Go to the Xilinx.com website
# https://www.xilinx.com/support/download.html
# Download the 2022.2 Unified Installer for Linux
# The link looks like:
# <Xilinx Unified Installer 2022.2: Linux Self Extracting Web Installer (BIN - 271.02 MB)>
# The download link will be similar to:
# https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2022.2_1014_8888_Lin64.bin
# - You will need to register on the website to download this file.

# Once the download is complete...
cd <location/of/downloaded/file>

# Extract the installer to a local temporary directory
PREFIX=/tmp/xilinx
VERSION=2022.2
INSTALLER="<downloaded/file>"  # This should match the download
INSTALLER_EXTRACTED="${PREFIX}/extracted"
mkdir $PREFIX
chown -R $USER:$USER $PREFIX $INSTALLER
chmod +x $INSTALLER
./$INSTALLER --keep --noexec --target $INSTALLER_EXTRACTED

# Now run this installer graphically, to create a new bundled-installer with the device support we need for the Arty-A7.
INSTALLER_BUNDLED="$PREFIX/bundled"
pushd $INSTALLER_EXTRACTED
./xsetup
popd
  • Running './xsetup' above should have popped up the graphical installation wizard.
    1. Page '<LANDING_PAGE>'
      1. Select 'Next >'
    2. Page 'Select Install Type'
      1. Enter email/password for 'User Authentication' (register on Xilinx.com)
      2. Select the radio-box 'Download Image (Install Seperately)'
      3. Select the download directory as '/tmp/xilinx/bundled' (the value from $INSTALLER_BUNDLED, See above)
      4. Under 'Download fields to create full image for selected platform(s)', select 'Linux' only.
      5. Under 'Image Contents', select 'Selected Product Only'
      6. Select 'Next >'
    3. Page 'Select Product to Install'
      1. Select the radio-box 'Vivado' only
      2. Select 'Next >'
    4. Page 'Select Edition to Install'
      1. Select the radio-box 'Vivado ML Standard'
      2. Select 'Next >'
    5. Page 'Vivado ML Standard'
      1. Ensure only the following boxes are selected....
        1. Design Tools - Vivado Design Suite - {Vivado, Vitis HLS}
        2. Devices - Production Devices - 7 Series - {Artix7, Kintex7, Spartan7}
        3. Installation Options
      2. Select 'Next >'
    6. Page 'Download Summary'
      1. Check the download is approx 13GB.
      2. Select 'Download'
# Now we have created a bundled installer for Vivado, we need to add this to the nix store

# The easiest way to get the data into the nix store is by creating an archive...
pushd $PREFIX
BUNDLED_ARCHIVE="$PREFIX/vivado_bundled.tar.gz"
# (You may need to install 'pigz' for this step, e.g. 'sudo apt install pigz')
tar cf $BUNDLED_ARCHIVE -I pigz --directory=$(dirname $INSTALLER_BUNDLED) ./$(basename $INSTALLER_BUNDLED)

# Now add using 'nix-prefetch-url'
VIVADO_BUNDLED_HASH=$(nix-prefetch-url --type sha256 file:$BUNDLED_ARCHIVE)

# The value of this hash will be needed for the next step.
echo $VIVADO_BUNDLED_HASH
popd

Install dependencies and activate our environment

We can use the nix flake.nix recipe to build our environment.

git clone [email protected]:lowRISC/ibex-demo-system.git
cd ibex-demo-system

# [OPTIONAL]
# Copy dependencies from a pre-prepared USB stick to compensate for bad internet
# The hash below is the expected hash of the lab dependencies
usb_path="<path/to/usb>" # e.g. "/media/harry/KINGSTON"
nix copy \
  --no-require-sigs \
  --from file://${usb_path}/nix/store/ \
  /nix/store/kx1qnhs2b6ikn5s4mj7jpj84rasqwc2h-labenv

pushd dependencies && nix flake update && popd && nix flake update
nix develop

# Once it completes,you should see the lowRISC logo, followed by...
# >> ------------------------------------------------- <<
# >> Welcome the the ibex-demo-system nix environment! <<
# >> ------------------------------------------------- <<

# You are now in a shell with all the tools required to do the lab.

# To exit this shell environment when you are done, simply run
exit

# Bonus Nix
# Use nix-tree to interactively examine all dependencies of the demo.
nix run nixpkgs#nix-tree -- .#devShells.x86_64-linux.default --derivation

Vivado-specific change (only needed if enabled in flake.nix):

# Run this before the `nix flake update` above.

# Update the flake.nix with the hash ($VIVADO_BUNDLED_HASH) of the vivado installer
# (We need to update just the sha256 hash input of requireFile function.)
sed -i -- "s|sha256\s=\s\".*\";|sha256 = \"$VIVADO_BUNDLED_HASH\";|g" dependencies/flake.nix

Native Python Environment

(NOT NEEDED IN THE CONTAINER ENVIRONMENT)

To install python dependencies use pip, you may wish to do this inside a virtual environment to avoid disturbing you current python setup (note it uses a lowRISC fork of edalize and FuseSoC so if you already use these a virtual environment is recommended):

# Setup python venv
python3 -m venv .venv
source .venv/bin/activate

# Install python requirements
pip3 install -r python-requirements.txt

You may need to run the last command twice if you get the following error: ERROR: Failed building wheel for fusesoc

Building Software

C stack

First the software must be built. This can be loaded into an FPGA to run on a synthesized Ibex processor, or passed to a verilator simulation model to be simulated on a PC.

mkdir sw/c/build
pushd sw/c/build
cmake ..
make
popd

Rust stack

pushd sw/rust
cargo build --bin led
popd

For more details, please refer to Ibex Rust stack.

Note the FPGA build relies on a fixed path to the initial binary (blank.vmem) so if you want to create your build directory elsewhere you need to adjust the path in ibex_demo_system.core

Building Simulation

The Demo System simulator binary can be built via FuseSoC. From the Ibex repository root run:

fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system

Running the Simulator

Having built the simulator and software, to simulate using Verilator we can use the following commands. <sw_elf_file> should be a path to an ELF file (or alternatively a vmem file) built as described above. Use ./sw/c/build/demo/hello_world/demo to run the demo binary.

Run from the repository root run:

# For example :
./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator \
  --meminit=ram,./sw/c/build/demo/hello_world/demo

# You need to substitute the <sw_elf_file> for a binary we have build above.
./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator [-t] --meminit=ram,<sw_elf_file>

Pass -t to get an FST trace of execution that can be viewed with GTKWave.

Simulation statistics
=====================
Executed cycles:  5899491
Wallclock time:   1.934 s
Simulation speed: 3.05041e+06 cycles/s (3050.41 kHz)

Performance Counters
====================
Cycles:                     457
NONE:                       0
Instructions Retired:       296
LSU Busy:                   108
Fetch Wait:                 20
Loads:                      53
Stores:                     55
Jumps:                      21
Conditional Branches:       12
Taken Conditional Branches: 7
Compressed Instructions:    164
Multiply Wait:              0
Divide Wait:                0

Building FPGA bitstream

FuseSoC handles the FPGA build. Vivado tools must be setup beforehand. From the repository root:

fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system

The default board is the Arty A7, but you can also use different synthesis targets. For example, to use the Sonata board change the target to synth_sonata.

Programming FPGA

To program the FPGA, either use FuseSoC again

fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:demo_system

# If the above does not work, try executing the programming operation manually with..
make -C ./build/lowrisc_ibex_demo_system_0/synth-vivado/ pgm

You can also use OpenFPGALoader, here are some example commands:

# Programming the Arty A7
./openFPGALoader -b arty_a7_35t build/lowrisc_ibex_demo_system_0/synth-vivado/lowrisc_ibex_demo_system_0.bit

# Programming the Sonata board
./openFPGALoader -c ft4232 build/lowrisc_ibex_demo_system_0/synth_sonata-vivado/lowrisc_ibex_demo_system_0.bit

Loading an application to the programmed FPGA

The util/load_demo_system.sh script can be used to load and run an application. You can choose to immediately run it or begin halted, allowing you to attach a debugger.

# Run demo
./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo
./util/load_demo_system.sh run ./sw/c/build/demo/lcd_st7735/lcd_st7735

# Load demo and start halted awaiting a debugger
./util/load_demo_system.sh halt ./sw/c/build/demo/hello_world/demo

# Run demo on the Sonata board
./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/sonata-openocd-cfg.tcl

To view terminal output use screen:

# Look in /dev to see available ttyUSB devices
screen /dev/ttyUSB1 115200

If you see an immediate [screen is terminating], it may mean that you need super user rights. In this case, you may try using sudo.

To exit from the screen command, you should press ctrl-a followed by k. You will need to confirm the exit by pressing y.

Debugging an application

Either load an application and halt (see above) or start a new OpenOCD instance:

openocd -f util/arty-a7-openocd-cfg.tcl

Then run GDB against the running binary and connect to localhost:3333 as a remote target:

riscv32-unknown-elf-gdb ./sw/c/build/demo/hello_world/demo

(gdb) target extended-remote localhost:3333

ibex-demo-system's People

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ibex-demo-system's Issues

Issues with using timer

Hi all, I'm using the hello_world demo. I'm want to print a pattern 1 times inside the main while loop, but the pattern is printed multiple times inside the loop. Below is my code. Any help will be appreciated. Thanks.
P/S: issue is about printing pattern drived by the value of flag:

      if (flag == 0) {
        // write_r_valid(1);
        // puts("\n");
        flag = 1;
        puts("/************/");
        // puthex(flag);
      }
      else {
        puts("/**_____**/");
      }
int8_t flag = 0;

int main(void) {
  install_exception_handler(UART_IRQ_NUM, &test_uart_irq_handler);

  uart_enable_rx_int();
  // This indicates how often the timer gets updated.
  timer_init();
  // timer_enable(5000000);
  // timer_enable(4000000);
  timer_enable(10000000);

  uint64_t last_elapsed_time = get_elapsed_time();

  // Reset green LEDs to having just one on
  set_outputs(GPIO_OUT, 0x10);  // Bottom 4 bits are LCD control as you can see in top_artya7.sv
  while (1) {
    uint64_t cur_time = get_elapsed_time();

    if (cur_time != last_elapsed_time) {
      last_elapsed_time = cur_time;

      // Disable interrupts whilst outputting to prevent output for RX IRQ
      // happening in the middle

      set_global_interrupt_enable(0);

      uint32_t in_val = read_gpio(GPIO_IN_DBNC);

      puts(" [OUTPUT] r_data: ");
      r_data = read_r_data();
      puthex(r_data);

      puts(" [OUTPUT] w_valid: ");
      w_valid = read_w_valid();
      puthex(w_valid);

      puts(" [OUTPUT] t_valid: ");
      t_valid = read_t_valid();
      puthex(t_valid);

      puts(" [OUTPUT] out_data: ");
      out_data = read_r_data(H_t_OUT_X4_1);
      puthex(out_data);
      puts("\n");

      if (flag == 0) {
        // write_r_valid(1);
        // puts("\n");
        flag = 1;
        puts("/************/");
        // puthex(flag);
      }
      else {
        puts("/**_____**/");
      }

      // Re-enable interrupts with output complete
      set_global_interrupt_enable(1);
      /*
        Display PWM - for testing the timer frequency
      */
      {
        // Cycling through green LEDs
        if (USE_GPIO_SHIFT_REG) {
          // Feed value of BTN0 into the shift register
          set_outputs(GPIO_OUT_SHIFT, in_val);
        } else {
          // Cycle through LEDs unless BTN0 is pressed
          uint32_t out_val = read_gpio(GPIO_OUT);
          out_val          = (out_val << 1) & GPIO_LED_MASK;
          if ((in_val & 0x1) || (out_val == 0)) {
            out_val = 0x10;
          }
          set_outputs(GPIO_OUT, out_val);
        }
      }
    }

  }
}

Here the output (printed UART)
image

Missing System Memory Map for Ibex Demo System

In the case of "Ibex Simple System (https://github.com/lowRISC/ibex/tree/master/examples/simple_system)", the memory map of the system is shown in the figure below:

image

However, I could not find a similar memory map, which shows where are the memory regions of the "Ibex Demo System" peripherals, such as GPIO, SPI, UART and also RAM etc. In the file "demo_system_regs.h", I have found the following values:

image

But is there a memory map (documentation), which shows the exact memory regions (start address, size, etc.) of the peripherals and RAM?

zmmul extension issue

Hi, I am getting the following error when building the "demo" C program using lowrisc's toolchain (lowrisc-toolchain-rv32imcb-20230427-1 version):

/home/unai/…/lowrisc-toolchain-rv32imcb-20230427-1/bin/../lib/gcc/riscv32-unknown-elf/10.2.0/../../../../riscv32-unknown-elf/bin/ld: -march=rv32i2p0_m2p0_c2p0_zmmul1p0: Invalid or unknown z ISA extension: 'zmmul'

/home/unai/…/lowrisc-toolchain-rv32imcb-20230427-1/bin/../lib/gcc/riscv32-unknown-elf/10.2.0/../../../../riscv32-unknown-elf/bin/ld: failed to merge target specific data of file ../../common/CMakeFiles/common.dir/demo_system.c.o

However, this problem doesn't show up when building the same program with the official RISC-V GCC toolchain in my path. I assume that this is intended to work, as the program that I am trying to compile is the demo program (hello_world).

Thank you in advance!

Debug the simulation and capturing the GPIO outputs

Hello, I'm working on a project to improve myself, and unfortunately, I don't have an FPGA, so I'm testing what I do in simulation.

As far as I understand, the Debug process only works on the FPGA, and the simulation only records UART outputs. Is there a way to debug in the simulation to check the changes in each step and record GPIO outputs to a file? Thank you.

Building Simulation

When I try to build the Simulator for "Ibex Demo System", using the command:
"fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system".

I got the following error mesage:
"""
INFO: Running pre_build script check_tool_requirements
INFO: Building simulation model
INFO: verilator -f lowrisc_ibex_demo_system_0.vc -DDISABLE_PRIM_CDC_RAND_DELAY --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 -CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_demo_system" -LDFLAGS "-pthread -lutil -lelf" -Wall -Wwarn-IMPERFECTSCH --unroll-count 72

ERROR: %Warning-GENUNNAMED: ../src/lowrisc_ibex_demo_system_core_0/rtl/system/ibex_demo_system.sv:475:12: Unnamed generate block 'genblk2' (IEEE 1800-2017 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
475 | end else begin
| ^~~~~
... For warning description see https://verilator.org/warn/GENUNNAMED?v=5.018
... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message.
%Warning-GENUNNAMED: ../src/lowrisc_ibex_demo_system_core_0/rtl/system/gpio.sv:39:3: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
39 | for (genvar i = 0; i < GpiWidth; i++) begin
| ^~~
%Warning-GENUNNAMED: ../src/lowrisc_ibex_demo_system_core_0/rtl/system/spi_host.sv:118:15: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
118 | if (CPHA) begin
| ^~~~~
%Warning-GENUNNAMED: ../src/lowrisc_ibex_demo_system_core_0/rtl/system/spi_host.sv:139:14: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
139 | end else begin
| ^~~~~
%Error: Exiting due to 4 warning(s)
make: *** [Makefile:16: Vibex_demo_system.mk] Error 1

ERROR: Failed to build lowrisc:ibex:demo_system:0 : '['make', '-j', '4']' exited with an error: 2

"""

Does anyone know the reason and have a solution? I would really appreciate it, thanks :)!

Sysnthesis failure with Vivado 2022.2

ERROR: [Synth 8-91] ambiguous clock in event control [/home/izi/VLSI/ibex-demo-system/build/lowrisc_ibex_demo_system_0/src/lowrisc_ibex_demo_system_core_0/rtl/system/gpio.sv:43]

The offending code is https://github.com/lowRISC/ibex-demo-system/blob/main/rtl/system/gpio.sv#L44
If the line was not supposed to have a reset, it should be placed into a separate always block without the reset edge in the sensitivity list. The current code seems to imply using reset as a clock.

Corrupted lowrisc_prim_abstract_xx RTL files

Hi, I am building the Ibex demo system in windows and successfully built the software. While running the command for synthesis

fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system

The output from command-line is as in the attached file - cmd_output.txt

This generated the prim_xx.sv files that are corrupted and providing syntax errors. I am attaching two of such generated files (uploading copied txt files since sv files cannot be uploaded) -
prim_and2.txt
prim_buf.txt

Could you please assist me with this issue?

`riscv32-unknown-elf-gcc` not found

I got a question by someone trying to run make and they were getting the following error:

[ 3%] Building C object common/CMakeFiles/common.dir/demo_system.c.o
/bin/sh: 1: riscv32-unknown-elf-gcc: not found make[2]: ***
[common/CMakeFiles/common.dir/build.make:76: common/CMakeFiles/common.dir/demo_system.c.o] Error 127 make[1]: ***
[CMakeFiles/Makefile2:209: common/CMakeFiles/common.dir/all] Error 2 make: ***
[Makefile:91: all] Error 2

This is usually because you need to install the software requirements: https://github.com/lowRISC/ibex-demo-system#software-requirements
This instructs you to download the lowRISC rv32imc toolchain from here: https://github.com/lowRISC/lowrisc-toolchains/releases
Also make sure that once you've extracted this, that you add the bin folder to your path.

Unable to run simulator for Hello World demo due to missing files and makefile error

hi everyone. As I was following the instructions to run the simulator, when I tried to run the command ./build/lowrisc_ibex_demo_system_0/simverilator/Vibex_demo_system \ --meminit=ram,./sw/c/build/demo/hello_world/demo, it produced the following errors, and I don't know how to fix the issues. My verilator version is 4.210.

ERROR: In file included from ../src/lowrisc_ibex_demo_system_0/dv/verilator/ibex_demo_system.cc:9:
./Vibex_demo_system__Syms.h:10:10: fatal error: verilated_heavy.h: No such file or directory
   10 | #include "verilated_heavy.h"
      |          ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [Vibex_demo_system.mk:120: ibex_demo_system.o] Error 1
make[1]: *** Waiting for unfinished jobs....
In file included from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilated_toplevel.h:21,
                 from ../src/lowrisc_ibex_demo_system_0/dv/verilator/ibex_demo_system.h:5,
                 from ../src/lowrisc_ibex_demo_system_0/dv/verilator/ibex_demo_system_main.cc:5:
./Vibex_demo_system.h:11:10: fatal error: verilated_heavy.h: No such file or directory
   11 | #include "verilated_heavy.h"
      |          ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [Vibex_demo_system.mk:122: ibex_demo_system_main.o] Error 1
In file included from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilated_toplevel.h:21,
                 from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilated_toplevel.cc:5:
./Vibex_demo_system.h:11:10: fatal error: verilated_heavy.h: No such file or directory
   11 | #include "verilated_heavy.h"
      |          ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [Vibex_demo_system.mk:116: verilated_toplevel.o] Error 1
In file included from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilated_toplevel.h:21,
                 from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilator_sim_ctrl.h:13,
                 from ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilator_sim_ctrl.cc:5:
./Vibex_demo_system.h:11:10: fatal error: verilated_heavy.h: No such file or directory
   11 | #include "verilated_heavy.h"
      |          ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [Vibex_demo_system.mk:118: verilator_sim_ctrl.o] Error 1
make: *** [Makefile:13: Vibex_demo_system] Error 2

ERROR: Failed to build lowrisc:ibex:demo_system:0 : '['make', '-j', '4']' exited with an error: 2

I am not sure if this is related, but when I tried to run the make command in the Building Software section for C stack, it produced these errors...

[ 93%] Linking C executable basic-passwdcheck
[ 93%] Built target basic-passwdcheck
[ 96%] Linking ASM executable blank
/usr/bin/objcopy: Unable to recognise the format of the input file `/home/aaron/Downloads/ibex-demo-system/sw/c/build/blank/blank'
make[2]: *** [blank/CMakeFiles/blank.dir/build.make:97: blank/blank] Error 1
make[2]: *** Deleting file 'blank/blank'
make[1]: *** [CMakeFiles/Makefile2:421: blank/CMakeFiles/blank.dir/all] Error 2
make: *** [Makefile:91: all] Error 2

load_demo_system.sh issue

Hello, i am trying to port the ibex_demo_system to a zedboard. I modified the top file and added the required pin constraint file and the bitstream generation is successful. However when running the load_demo_system.sh i encounter the next error:

./util/load_demo_system2.sh run ./sw/c/build/demo/hello_world/demo

Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read http://openocd.org/doc/doxygen/bugs.html
User : 13 1 options.c:63 configuration_output_handler(): debug_level: 3
User : 14 1 options.c:63 configuration_output_handler(): 
Debug: 15 1 options.c:244 add_default_dirs(): bindir=/usr/bin
Debug: 16 1 options.c:245 add_default_dirs(): pkgdatadir=/usr/share/openocd
Debug: 17 1 options.c:246 add_default_dirs(): exepath=/usr/bin
Debug: 18 1 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 19 1 configuration.c:42 add_script_search_dir(): adding /home/jorge/.config/openocd
Debug: 20 1 configuration.c:42 add_script_search_dir(): adding /home/jorge/.openocd
Debug: 21 1 configuration.c:42 add_script_search_dir(): adding /usr/bin/../share/openocd/site
Debug: 22 1 configuration.c:42 add_script_search_dir(): adding /usr/bin/../share/openocd/scripts
Debug: 23 1 configuration.c:97 find_file(): found /home/jorge/ibex-demo-system/util/zedboard-openocd-cfg.tcl
Debug: 24 1 command.c:146 script_debug(): command - adapter driver ftdi
Debug: 26 1 command.c:146 script_debug(): command - transport select jtag
Debug: 27 1 command.c:146 script_debug(): command - ftdi_device_desc Digilent USB Device
Debug: 29 1 command.c:146 script_debug(): command - ftdi_vid_pid 0x0403 0x6014
Debug: 31 1 command.c:146 script_debug(): command - ftdi_layout_init 0x2088 0x3f8b
Debug: 33 1 command.c:146 script_debug(): command - ftdi_layout_signal nSRST -data 0x2000
Debug: 35 1 command.c:146 script_debug(): command - ftdi_layout_signal GPIO2 -data 0x2000
Debug: 37 1 command.c:146 script_debug(): command - ftdi_layout_signal GPIO1 -data 0x0200
Debug: 39 1 command.c:146 script_debug(): command - ftdi_layout_signal GPIO0 -data 0x0100
Debug: 41 1 command.c:146 script_debug(): command - jtag newtap riscv cpu -irlen 6 -expected-id 0x03727093
Debug: 42 1 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 4 params
Debug: 43 1 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 44 1 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 45 1 core.c:1484 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 0, irlen 6, capture: 0x1 mask: 0x3
Debug: 46 2 command.c:146 script_debug(): command - jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477
Debug: 47 2 tcl.c:571 jim_newtap_cmd(): Creating New Tap, Chip: arm_unused, Tap: tap, Dotted: arm_unused.tap, 4 params
Debug: 48 2 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 49 2 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 50 2 core.c:1484 jtag_tap_init(): Created Tap: arm_unused.tap @ abs position 1, irlen 4, capture: 0x1 mask: 0x3
Debug: 51 2 command.c:146 script_debug(): command - target create riscv.cpu riscv -chain-position riscv.cpu -coreid 0x3e0
Debug: 52 2 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas
Debug: 53 2 command.c:146 script_debug(): command - riscv set_ir idcode 0x09
Debug: 55 2 command.c:146 script_debug(): command - riscv set_ir dtmcs 0x22
Debug: 57 2 command.c:146 script_debug(): command - riscv set_ir dmi 0x23
Debug: 59 2 command.c:146 script_debug(): command - adapter speed 1000
Debug: 61 2 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 62 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 63 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 64 2 command.c:146 script_debug(): command - reset_config none
Debug: 66 2 command.c:146 script_debug(): command - init
Debug: 68 2 command.c:146 script_debug(): command - target init
Debug: 70 2 command.c:146 script_debug(): command - target names
Debug: 71 2 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-flash-erase-start
Debug: 72 2 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 73 2 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-flash-write-end
Debug: 74 2 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 75 2 command.c:146 script_debug(): command - riscv.cpu cget -event gdb-attach
Debug: 76 2 command.c:146 script_debug(): command - riscv.cpu configure -event gdb-attach halt 1000
Debug: 77 2 target.c:1639 handle_target_init_command(): Initializing targets...
Debug: 78 2 riscv.c:427 riscv_init_target(): riscv_init_target()
Debug: 79 2 semihosting_common.c:99 semihosting_common_init():  
Debug: 80 2 ftdi.c:650 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 81 9 mpsse.c:422 mpsse_purge(): -
Debug: 82 9 mpsse.c:703 mpsse_loopback_config(): off
Debug: 83 9 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 84 9 mpsse.c:740 mpsse_rtck_config(): off
Debug: 85 9 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 86 9 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 87 10 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 88 10 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 89 10 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 90 10 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
Debug: 91 10 mpsse.c:740 mpsse_rtck_config(): off
Debug: 92 10 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 93 10 mpsse.c:709 mpsse_set_divisor(): 29
Debug: 94 10 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
Debug: 95 10 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 96 10 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 97 10 core.c:1565 adapter_init(): clock speed 1000 kHz
Debug: 98 10 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 99 10 command.c:146 script_debug(): command - transport init
Debug: 101 10 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 102 10 core.c:830 jtag_add_reset(): SRST line released
Debug: 103 10 core.c:855 jtag_add_reset(): TRST line released
Debug: 104 10 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 105 10 command.c:146 script_debug(): command - jtag arp_init
Debug: 106 10 core.c:1578 jtag_init_inner(): Init JTAG chain
Debug: 107 10 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 108 10 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 109 10 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 110 11 core.c:1142 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x03727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x0)
Info : 111 11 core.c:1142 jtag_examine_chain_display(): JTAG tap: arm_unused.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Debug: 112 11 core.c:1374 jtag_validate_ircapture(): IR capture validation scan
Debug: 113 11 core.c:1431 jtag_validate_ircapture(): riscv.cpu: IR capture 0x35
Debug: 114 11 core.c:1431 jtag_validate_ircapture(): arm_unused.tap: IR capture 0x01
Debug: 115 11 command.c:146 script_debug(): command - dap init
Debug: 117 11 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
Debug: 118 11 openocd.c:160 handle_init_command(): Examining targets...
Debug: 119 11 target.c:1825 target_call_event_callbacks(): target event 19 (examine-start) for core riscv.cpu
Debug: 120 11 riscv.c:965 riscv_examine(): riscv_examine()
Debug: 121 11 riscv.c:399 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 122 11 riscv.c:975 riscv_examine(): dtmcontrol=0x1071
Debug: 123 11 riscv.c:977 riscv_examine():   version=0x1
Debug: 124 11 riscv-013.c:2013 init_target(): init
Debug: 125 11 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 126 11 riscv-013.c:1572 examine(): dtmcontrol=0x1071
Debug: 127 11 riscv-013.c:1573 examine():   dmireset=0
Debug: 128 11 riscv-013.c:1574 examine():   idle=1
Debug: 129 11 riscv-013.c:1575 examine():   dmistat=0
Debug: 130 11 riscv-013.c:1576 examine():   abits=7
Debug: 131 11 riscv-013.c:1577 examine():   version=1
Debug: 132 11 riscv-013.c:259 get_dm(): [992] Allocating new DM
Debug: 133 11 riscv-013.c:399 scan(): 41b w 00000000 @10 -> + 00000000 @00; 0i
Debug: 134 11 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 0i
Debug: 135 12 riscv-013.c:399 scan(): 41b w 00000001 @10 -> b 00000000 @10; 0i
Debug: 136 12 riscv-013.c:409 scan():  dmactive -> 
Debug: 137 12 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 138 12 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 139 12 riscv-013.c:399 scan(): 41b w 00000001 @10 -> + 00000000 @10; 1i
Debug: 140 12 riscv-013.c:409 scan():  dmactive -> 
Debug: 141 12 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 1i
Debug: 142 12 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 143 12 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 144 12 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 2i
Debug: 145 12 riscv-013.c:399 scan(): 41b w 07ffffc1 @10 -> b 00000000 @10; 2i
Debug: 146 12 riscv-013.c:409 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 147 12 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 148 13 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 149 13 riscv-013.c:399 scan(): 41b w 07ffffc1 @10 -> + 00000000 @10; 3i
Debug: 150 13 riscv-013.c:409 scan():  hasel hartselhi=1023 hartsello=1023 dmactive -> 
Debug: 151 13 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 3i
Debug: 152 13 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 153 13 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 154 13 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 4i
Debug: 155 13 riscv-013.c:399 scan(): 41b r 00000000 @10 -> b 00000000 @10; 4i
Debug: 156 13 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=5, ac_busy_delay=0
Debug: 157 14 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 158 14 riscv-013.c:399 scan(): 41b r 00000000 @10 -> + 00000000 @10; 5i
Debug: 159 14 riscv-013.c:399 scan(): 41b - 00000000 @10 -> b 00000000 @10; 5i
Debug: 160 14 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=6, ac_busy_delay=0
Debug: 161 14 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 162 14 riscv-013.c:399 scan(): 41b - 00000000 @10 -> + 00000000 @10; 6i
Error: 163 14 riscv-013.c:1612 examine(): Debug Module did not become active. dmcontrol=0x0
Debug: 164 14 target.c:1825 target_call_event_callbacks(): target event 20 (examine-fail) for core riscv.cpu
Warn : 165 14 target.c:782 target_examine(): target riscv.cpu examination failed
Debug: 166 14 openocd.c:162 handle_init_command(): target examination failed
Debug: 167 14 command.c:146 script_debug(): command - flash init
Debug: 169 14 tcl.c:1385 handle_flash_init_command(): Initializing flash devices...
Debug: 170 14 command.c:146 script_debug(): command - nand init
Debug: 172 14 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 173 14 command.c:146 script_debug(): command - pld init
Debug: 175 14 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Info : 176 14 gdb_server.c:3503 gdb_target_start(): starting gdb server for riscv.cpu on 3333
Info : 177 14 server.c:311 add_service(): Listening on port 3333 for gdb connections
Debug: 178 14 command.c:146 script_debug(): command - halt
Debug: 180 14 target.c:3260 handle_halt_command(): -
Error: 181 14 target.c:579 target_halt(): Target not examined yet
Debug: 182 14 command.c:628 run_command(): Command 'halt' failed with error code -4
User : 183 14 command.c:694 command_run_line(): 
Debug: 184 14 riscv.c:472 riscv_deinit_target(): riscv_deinit_target()
Debug: 185 14 riscv-013.c:1530 deinit_target(): riscv_deinit_target()
Debug: 186 14 target.c:2172 target_free_all_working_areas_restore(): freeing all working areas

i modified the script whit the next configuration:

adapter driver ftdi
transport select jtag

ftdi_device_desc "Digilent USB Device"
ftdi_vid_pid 0x0403 0x6014
#ftdi_channel 0
#ftdi_layout_init 0x0088 0x008b
#reset_config srst_only srst_push_pull
#ftdi_tdo_sample_edge falling
ftdi_layout_init 0x2088 0x3f8b
ftdi_layout_signal nSRST -data 0x2000
ftdi_layout_signal GPIO2 -data 0x2000
ftdi_layout_signal GPIO1 -data 0x0200
ftdi_layout_signal GPIO0 -data 0x0100


#Configure JTAG chain and the target processor
set _CHIPNAME riscv

#Configure JTAG expected ID
#Zedboard
set _EXPECTED_ID 0x03727093


#jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version
#set _TARGETNAME $_CHIPNAME.cpu
#target create $_TARGETNAME riscv -chain-position $_TARGETNAME

jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID
jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0

riscv set_ir idcode 0x09
riscv set_ir dtmcs 0x22
riscv set_ir dmi 0x23

adapter speed 1000

#riscv set_prefer_sba on
#gdb_report_data_abort enable
#gdb_report_register_access_error enable
#gdb_breakpoint_override hard

reset_config none

init
halt

The issue seems to be that the debug module doesn't activate which i don't know how to modify. Any help would be appreciated either some info on how the debug unit works or something.

Issues building/running Ibex Demo System on Arty35

I had to resolve two issues while trying to get the Ibex Demo System running on my Arty35 board, following the steps in the Readme.md; I hope the following will save time for anyone else who tries this, and can be incorporated into the Readme.md via an appropriate update.

First Issue: the FPGA bitstream built via FuseSoC absolutely wasn't talking to OpenOCD at all. Explanation: the debug module was not being built correctly, because the FuseSoC installed via the python_requirements.txt file doesn't allow for a 'Flags' item in a 'Target' section within a .core file. This causes incorrect fileset selection for the Debug module: the Arty build needs to read the flag 'use_bscane2_tap' as True, but with 'Flags' unrecognised that's not happening. A quick workaround is simply to tweak the .core file so it selects unconditionally the fileset containing the bscane tap module. A cleaner resolution for the long term probably needs to be decided by a maintainer of the lowRISC fusesoc repo who knows how the various branches are being used, but here's the gist of the problem: the file fusesoc/capi2/core.py creates the Core() class from the string 'description', and there's a crucial difference between the OT and Main branches: in Main, the Target section is defined to allow an entry with name 'flags' at line 799, within .dicts; by contrast, in OT, the Target section does not have any .dicts at all, and doesn't have 'flags' in .members or .lists either - hence the rejection of the keyword 'flags'. Options would include (a) updating python_requirements.txt to select Main branch rather than OT, IF that would work - haven't tried it (b) updating the OT capi2/core.py file to add the missing 'flags' entry IF that doesn't break things for someone else(c) some other solution.

Second Issue: The script used to run the demo program uses an option set_prefer_sba which is not known to OpenOCD v.012, and appears to make that tool get stuck in and endless loop while communicating with Arty via JTAG. A comment in the source repo says this option is now deprecated, so I tried simply commenting it out, and confirmed this lets the demo run successfully.

Issue with Vtop_verilator when running simulator. ; Replaced with Vibex_demo_system

Hello, so as i was going through the procedures, i was trying to run the simulator by running ./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator \ --meminit=ram,./sw/c/build/demo/hello_world/demo , as stated. However, for some reason it produced this error:
./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator: No such file or directory
So what i did was i went to the sim_verilator directory to find Vtop_verilator. Then i found that there is an executable file named Vibex_demo_system. I replaced Vtop_verilator with Vibex_demo_system, and re-run the command.
Then it worked as intended. I would like to know if this is normal? Or there is a mix-up somewhere?

Error while building simulation

While building simulation from Ibex Repo folder, I got this error.

sh-5.0$ fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
ERROR: 'lowrisc:ibex:demo_system' or any of its dependencies requires 'demo_system', but this core was not found

How to fix this issue?

Can't build software, cmake file not found

Hi, i was setting the system up, succesfully got docker to setup...

aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system$ sudo docker run -it --rm \
>   -p 6080:6080 \
>   -p 3333:3333 \
>   -v $(pwd):/home/dev/demo:Z \
>   ibex
[sudo] password for aaron: 
Please be aware that you are exposing your VNC server to all users on the
local machine. These users can access your server without authentication!
/usr/bin/xauth:  file /home/dev/.Xauthority does not exist

New '33f8941bd738:1 (dev)' desktop at :1 on machine 33f8941bd738

Starting applications specified in startxfce4
Log file is /home/dev/.vnc/33f8941bd738:1.log

Use xtigervncviewer -SecurityTypes None :1 to connect to the VNC server.

WebSocket server settings:
  - Listen on :6080
  - Web server. Web root: /usr/share/novnc
  - SSL/TLS support
  - proxying from :6080 to localhost:5901
172.17.0.1 - - [20/Dec/2023 07:34:50] 172.17.0.1: Plain non-SSL (ws://) WebSocket connection
172.17.0.1 - - [20/Dec/2023 07:34:50] 172.17.0.1: Path: '/websockify'
172.17.0.1 - - [20/Dec/2023 07:34:50] connecting to: localhost:5901

My issue is that, i could not run this set of commands.

cd /home/dev/demo
mkdir -p sw/build
pushd sw/build
cmake ..
make
popd

It produced this set of errors,

aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system$ cd /home/dev/demo
cmake ..
make
popdbash: cd: /home/dev/demo: No such file or directory
aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system$ mkdir -p sw/build
aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system$ pushd sw/build
~/Downloads/ibex-demo-system/sw/build ~/Downloads/ibex-demo-system ~/Downloads/ibex-demo-system/sw/build ~/Downloads/ibex-demo-system ~ ~
aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system/sw/build$ cmake ..
CMake Error: The source directory "/home/aaron/Downloads/ibex-demo-system/sw" does not appear to contain CMakeLists.txt.
Specify --help for usage, or press the help button on the CMake GUI.
aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system/sw/build$ make
make: *** No targets specified and no makefile found.  Stop.
aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system/sw/build$ popd
~/Downloads/ibex-demo-system ~/Downloads/ibex-demo-system/sw/build ~/Downloads/ibex-demo-system ~ ~

I not sure what is dev in the cd /home/dev/demo command suppose to be. There is no cmake file in sw/build

aaron@aaron-TravelMate-P238-M:~/Downloads/ibex-demo-system/sw$ ls
build  c  common  rust

Problem with loading hello world demo

I am executing the commands as said on the README and I'm getting the following error
after executing ./util/load_demo_system.sh run ./sw/build/demo/hello_world/demo
::
::

Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
force hard breakpoints
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1)
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

Aliasing problem of Python3 on Windows and unable to create new project file using Fusesoc on Windows

Hello, I am attempting to clone the "ibex-demo-system" repository and set up a project on Xilinx Vivado for FPGA synthesis on the Arty Board. I am running "fusesoc" from the "ibex core" repository on the Anaconda command prompt. However, I encountered errors related to aliasing "python3" on Windows. Unlike other platforms, Windows saves executable files as "python.exe" by default instead of "python3". Could you kindly assist me in creating an alias for "python3" on Windows, so I can resolve these issues?

(ibex_env) D:\Users\DELL\Downloads\ibex_demo_system>fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:demo_system
←[1;37mINFO: Preparing lowrisc:dv:crypto_prince_ref:0.1←[0m
←[1;37mINFO: Preparing lowrisc:dv:dv_fcov_macros:0←[0m
←[1;37mINFO: Preparing lowrisc:dv:dv_macros:0←[0m
←[1;37mINFO: Preparing lowrisc:dv:secded_enc:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:ibex_pkg:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:assert:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:cipher_pkg:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:primgen:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_1p_pkg:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_2p_pkg:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:secded:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:util_get_scramble_params:0←[0m
←[1;37mINFO: Preparing lowrisc:tool:check_tool_requirements:0.1←[0m
←[1;37mINFO: Preparing lowrisc:dv:scramble_model:0←[0m
←[1;37mINFO: Preparing lowrisc:dv_verilator:memutil_dpi:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:ibex_icache:0.1←[0m
←[1;37mINFO: Preparing lowrisc:ibex:rv_timer:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:cdc_rand_delay:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:cipher:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:lfsr:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:prim_pkg:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:util:0.1←[0m
←[1;37mINFO: Preparing lowrisc:dv_verilator:memutil_dpi_scrambled:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:buf:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:clock_gating:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:clock_inv:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:clock_mux2:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:flop:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:onehot_check:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_1p:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_2p:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:fpga_xilinx_shared:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:ibex_core:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:flop_2sync:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_1p_adv:0.1←[0m
←[1;37mINFO: Preparing lowrisc:prim:fifo:0←[0m
←[1;37mINFO: Preparing lowrisc:prim:ram_1p_scr:0.1←[0m
←[1;37mINFO: Preparing lowrisc:ibex:ibex_top:0.1←[0m
←[1;37mINFO: Preparing pulp:riscv:debug_module:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:demo_system_core:0←[0m
←[1;37mINFO: Preparing lowrisc:ibex:demo_system:0←[0m
←[1;37mINFO: Generating lowrisc:prim:prim_pkg-impl:0.1←[0m
Traceback (most recent call last):
File "D:\Users\DELL\Downloads\ibex_demo_system\vendor\lowrisc_ibex\vendor\lowrisc_ip\ip\prim\util/primgen.py", line 12, in
from mako.template import Template
ModuleNotFoundError: No module named 'mako'
←[1;31mERROR: Setup failed : "python3 D:\Users\DELL\Downloads\ibex_demo_system\vendor\lowrisc_ibex\vendor\lowrisc_ip\ip\prim\util/primgen.py D:\Users\DELL\Downloads\ibex_demo_system\build\lowrisc_ibex_demo_system_0\synth-vivado\generated\lowrisc_prim_prim_pkg-impl_0.1\impl_input.yml" exited with an error code. See stderr for details.←[0m

(ibex_env) D:\Users\DELL\Downloads\ibex_demo_system>
(ibex_env) D:\Users\DELL\Downloads\ibex_demo_system># If the above does not work, try executing the programming operation manually with..
'#' is not recognized as an internal or external command,
operable program or batch file.

(ibex_env) D:\Users\DELL\Downloads\ibex_demo_system>make -C ./build/lowrisc_ibex_demo_system_0/synth-vivado/ pgm
make: Entering directory 'D:/Users/DELL/Downloads/ibex_demo_system/build/lowrisc_ibex_demo_system_0/synth-vivado'
make: *** No rule to make target 'pgm'. Stop.
make: Leaving directory 'D:/Users/DELL/Downloads/ibex_demo_system/build/lowrisc_ibex_demo_system_0/synth-vivado'

Cannot run the Docker container on Windows following the instructions in the main readme file

First of all, I had to clear a smaller issue to find the container in the first place. This instruction in the readme says there is a prebuilt container ready, but then it does not mention where it is located:

There is a prebuilt container of tools available you may want to use to get started quickly. There are instructions for building the container for either Docker/Podman located in ./container/README.md.

By looking through the issues and going to the releases I managed to find a .tar.gz container in the latest release. I downloaded it and extracted the .tar file into my ibex-demo-system local cloned repository.

Next, I ran these commands from the Windows section in an administrator cmd:

cd "C:\Program Files\Docker\Docker" .\DockerCli.exe -SwitchLinuxEngine

Then, this instruction from the readme is not very clear on where to run the next commands, so i changed directories back to the ibex-demo-system directory:

In case you have a tarball of the docker image, run:

Finally, I ran this code with the name of the .tar file changed to the one from the release:

docker load -i ibex-demo-system-docker.tar

And that gave me the following error:

error during connect: in the default daemon configuration on Windows, the docker client must be run with elevated privileges to connect: Post "http://%2F%2F.%2Fpipe%2Fdocker_engine/v1.24/images/load?quiet=0": open //./pipe/docker_engine: The system cannot find the file specified.

I find it weird that it asks about elevated privileges as i am in an administrator cmd window.

Ibex Demo System Tracer

Unlike the Ibex Simple System, the Ibex Demo System doesn't generate a log of executed instructions (execution trace) on using the plusarg ibex_tracer_enable=1. Is there any way of obtaining all traced instructions in a log file, the same way as in the Ibex Simple System? Any help is appreciated. Thank you.

About SRAMInitFile

SRAMInitFile is a localparam defined in ibex_demo_system.sv. I'm sure how to use that. Is this can initial u_ram in implementation phase of vivado, or this just for simulation with verilator ? Also, I see BRAM utilization resources of vivado changes when I change the size of ram_2p, can we initialize the data inside the BRAM after performming the implementation in vivado or something inside the bitstream, not use the application code (i.e C/C++) to control a cores (PS) to write to BRAM. Thanks

debug module

i am trying to program / load an executable into ibex_demo_system following the commands in github on Arty-A7.
The FPGA is programmed ok but on last command ( ./util/load_demo_system.sh run ./sw/hello_test/hello_test.elf) it seems that openocd cant halt ibex. I am attaching the screen log at the end. Have you see something in the past? any Hint?

Open On-Chip Debugger 0.12.0+dev-00094-gb6b4f9d46 (2023-03-23-14:56)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
force hard breakpoints
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Info : datacount=2 progbufsize=8
Error: unable to halt hart 0
Error: dmcontrol=0x80000001
Error: dmstatus =0x00000c82
Error: Fatal: Hart 0 failed to halt during examine()
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

The pip install setup for the container seems incomplete as fusesoc throws an error on a clean run.

When creating the container fresh after cloning this repository and when into the VNC viewer, running the fusesoc command:
fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
results in an error:
`ERROR: Traceback (most recent call last):
File "util/check_tool_requirements.py", line 10, in
from packaging.version import Version
ModuleNotFoundError: No module named 'packaging'

ERROR: Failed to build lowrisc:ibex:demo_system:0 : pre_build script 'check_tool_requirements': ['python3', 'util/check_tool_requirements.py'] exited with error code 1`

After running pip install packaging the fusesoc command runs without errors

Can't build docker Container

When I build a docker container following the instructions in https://github.com/lowRISC/ibex-demo-system/tree/main/container, I have the following error.
My system is Mac.
It seems there is no python3 in the docker environment /usr/bin/env.

>  => [internal] load build definition from Dockerfile                                                                                                  0.0s
 => => transferring dockerfile: 3.88kB                                                                                                                0.0s
 => [internal] load .dockerignore                                                                                                                     0.0s
 => => transferring context: 2B                                                                                                                       0.0s
 => [internal] load metadata for docker.io/library/ubuntu:20.04                                                                                       2.0s
 => [ 1/17] FROM docker.io/library/ubuntu:20.04@sha256:f2034e7195f61334e6caff6ecf2e965f92d11e888309065da85ff50c617732b8                               0.0s
 => [internal] load build context                                                                                                                     0.0s
 => => transferring context: 543B                                                                                                                     0.0s
 => CACHED [ 2/17] RUN ln -sf /bin/bash /bin/sh                                                                                                       0.0s
 => CACHED [ 3/17] RUN OBS_URL="https://download.opensuse.org/repositories";     OBS_PATH="/home:/phiwag:/edatools/xUbuntu_20.04";     REPO_URL="${O  0.0s
 => CACHED [ 4/17] COPY container/apt-requirements.txt /tmp/apt-requirements.txt                                                                      0.0s
 => CACHED [ 5/17] RUN echo "verilator-4.210" >> /tmp/apt-requirements.txt     && sed -i -e '/^$/d' -e '/^#/D' -e 's/#.*//' /tmp/apt-requirements.tx  0.0s
 => CACHED [ 6/17] COPY container/get-toolchain.py /tmp/get-toolchain.py                                                                              0.0s
 => ERROR [ 7/17] RUN /tmp/get-toolchain.py -r 20220210-1     && rm -f /tmp/get-toolchain.py                                                          0.2s
------                                                                                                                                                     
 > [ 7/17] RUN /tmp/get-toolchain.py -r 20220210-1     && rm -f /tmp/get-toolchain.py:
0.180 /usr/bin/env: 'python3': No such file or directory
------
Dockerfile:57
--------------------
  56 |     COPY container/get-toolchain.py /tmp/get-toolchain.py
  57 | >>> RUN /tmp/get-toolchain.py -r ${RISCV_TOOLCHAIN_RELEASE_TAG} \
  58 | >>>     && rm -f /tmp/get-toolchain.py
  59 |     ENV PATH "/tools/riscv/bin:${PATH}"
--------------------
ERROR: failed to solve: process "/bin/sh -c /tmp/get-toolchain.py -r ${RISCV_TOOLCHAIN_RELEASE_TAG}     && rm -f /tmp/get-toolchain.py" did not complete successfully: exit code: 127

Unable to create a project file for synthesis.

Hi, I am trying to replicate the ibex demo. Intend to create a Vivado project for FPGA synthesis for Arty board. Run fusesoc from Ibex core repository with the command:

fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system`
However get the following error log:
`WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_xnor2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_and2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_usb_diff_rx.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_pad_wrapper.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core: 
Error validating data.filesets.files_rtl.depend must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lfsr.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_msb_extend.core: 
Error validating data.filesets.files_ascentlint_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_xnor2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_ram_1p_adv.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_mubi.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_pad_wrapper_pkg.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_ram_2p.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_sync.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_rom.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_buf.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_flop.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_and_hardened.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_xor2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_or_hardened.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_rst_sync.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_dec.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_secded.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_flop_en.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_otp.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_clock_buf.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_and2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_pad_attr.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_clock_inv.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_flash.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_clock_gating.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_ram_1p_pkg.core: 
Error validating data.filesets.files_rtl.depend must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_combine.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_xoshiro256pp.core: 
Error validating data.filesets.files_ascentlint_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_ram_1p.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_blanker.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_ram_2p_pkg.core: 
Error validating data.filesets.files_rtl.depend must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim/prim_lc_sender.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_and2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop_en.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_xor2.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
WARNING: Parse error. Ignoring file ./vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_attr.core: 
Error validating data.filesets.files_verilator_waiver.files must be array
ERROR: 'lowrisc:ibex:demo_system' or any of its dependencies requires 'demo_system', but this core was not found

Building Software

Hello, I have executed the command cmake .. successfully.

However, I once execute the make command, the process will be executed till [100%], but then I got the following error:

"""
[ 93%] Linking C executable basic-passwdcheck
[ 93%] Built target basic-passwdcheck
Scanning dependencies of target blank
[ 96%] Building ASM object blank/CMakeFiles/blank.dir/blank.S.obj
[100%] Linking ASM executable blank
/usr/bin/objcopy: Unable to recognise the format of the input file `path_to_repo/ibex-demo-system/sw/c/build/blank/blank'
make[2]: *** [blank/CMakeFiles/blank.dir/build.make:97: blank/blank] Error 1
make[2]: *** Deleting file 'blank/blank'
make[1]: *** [CMakeFiles/Makefile2:421: blank/CMakeFiles/blank.dir/all] Error 2
make: *** [Makefile:91: all] Error 2
"""

I can see the binaries of all demos (basic-passwdcheck, hello_world. lcd_st7735, simpleserial-aes) in their respective folders. But what is the meaning of the last error and is it important?

I would appreciate, if someone knowing the reason of this issue, can explain.

Thanks in advance!

A basic peripheral to write ASCII output to a file and halt simulation from software

In the documentation it is written that there is a basic peripheral to write ASCII output to a file and halt simulation from software. I assume that this is only used in case of a Verilator right? In case of a real target, FPGA, the ASCII output will be sent to the UART and not written to the ".log" file.

image

Functions like puts(), puthex(), putchar() work perfectly fine for the "Ibex Simple System (https://github.com/lowRISC/ibex/blob/master/examples/simple_system/README.md)" when simulating it on the Verilator. The output is written to file "ibex_simple_system.log":

image

However, the same functions do not write to the file "ibex_demo_system.log", which is still empty after the simulation. Am I doing or understanding wrong or is there a issue there?

image

Thanks in advance!

Unable to build FPGA Bitstream

HI. I was following the instructions on the main page to build the system. When i run fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system, it says:

ERROR: make: vivado: No such file or directory
make: *** [Makefile:8: lowrisc_ibex_demo_system_0.xpr] Error 127

ERROR: Failed to build lowrisc:ibex:demo_system:0 : '['make']' exited with an error: 2

I have installed my vivado at opt/Xilinx. I not sure what i should do to provide a new directory for it to search for vivado. Also, since opt/XIlinx is the default directory, but didn't it work?

Unable to load a new program using OpenOCD if the current program doesn't run in an infinite loop

I created a new test program and used the CMake build script in the sw directory to build it. However, after the FPGA is programmed, the load_demo_system.sh script only works the first time and consistently fails on subsequent attempts. (Note: I have adapted the design to work on the PYNQ-Z2 board, but that shouldn't be the root of the problem as the script worked the first time.)

Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'ftdi device_desc' not 'ftdi_device_desc'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi channel' not 'ftdi_channel'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
Warn : `riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.
force hard breakpoints
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x23727093 (mfg: 0x049 (Xilinx), part: 0x3727, ver: 0x2)
Info : JTAG tap: arm_unused.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Info : datacount=2 progbufsize=8
Error: unable to halt hart 0
Error:   dmcontrol=0x80000001
Error:   dmstatus =0x00000c82
Error: Fatal: Hart 0 failed to halt during examine()
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

The reason, as far as I can tell, is that my program returns 0 and transfers control back to crt0.S instead of running in an infinite loop like the other demo program. The problem is solved by adding a while(1) loop at the end of the program, although a sleep_loop in crt0.S should have also worked. Further investigation indicates that the design appears to be stopped after writing 1 to SIM_CTRL_BASE + SIM_CTRL_CTRL, preventing the design from receiving commands from openocd until the FPGA is reprogrammed.

main_entry:
  /* jump to main program entry point (argc = argv = 0) */
  addi x10, x0, 0
  addi x11, x0, 0
  jal x1, main

  /* Halt simulation */
  li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
  li x6, 1
  sw x6, 0(x5)

  /* If execution ends up here just put the core to sleep */
sleep_loop:
  wfi
  j sleep_loop

Should we put the code to halt simulation under #ifdef, which can be controlled by the CMake option? Or should we make a modification such that the design can only be halted in the simulator but not in the FPGA? Thank you for your suggestion, and either way, I would be happy to create a PR for the fix.

#ifdef HALT_SIM_WHEN_EXIT
  /* Halt simulation */
  li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
  li x6, 1
  sw x6, 0(x5)
#endif

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